近年來，隨著先進封裝技術的進步，使得佈局規模迅速地擴大；且佈局繞線規則及限制越來越複雜，包括允許任意角度繞線，和非一致性繞線間距限制。此外，隨著高速產品的發展，嚴格的時序規範變得至關重要，因而延遲匹配(Delay Matching)在封裝上成為不可忽視的問題。在印刷電路板(Printed Circuit Board, PCB)中，延遲匹配問題已有被廣泛地研究，但在先進封裝中尚未有研究去解決此問題；該問題涉及複雜繞線規則和佈局更為壅塞(Congestion)，導致高計算成本。在本論文中，我們提出了對先進封裝中延遲匹配繞線問題的解決方法，該方法將常用的手風琴(Accordioon)、長號(Trombone)和鋸齒(Sawtooth)型的迂迴繞線與無網格(Gridless)繞線相結合。這些迂迴繞線模式常用於調整線長，同時能保持信號完整性。我們的方法在全域繞線(Global Routing)階段引入延遲匹配意識，以減輕密集繞線群組的擁塞問題。在細部繞線後(Post-Detailed Routing)，我們利用基於滑動視窗的方法檢測無違反設計規則的可繞線區域；並提出了重新分配繞線資源的方法，以避免並行匯流排(Bus)繞線中的擁塞問題。最後，我們開發了基於圖形的繞線方法，以獲取繞線結果並調整銳角信號線，以提高設計可製造性。實驗結果顯示我們提出的演算法的穩健性和有效性，並且我們的方法同樣適用於印刷電路板中。

As advanced package technology evolves, design scales are rapidly expanding, and routing rules are becoming more complex, including any-angle routing and non-default wire spacing. Moreover, as high-speed applications advance, strict timing specifications for packages have become crucial, making delay matching an important consideration. In printed circuit board (PCB), the delay-matching problem has been well studied, but no previous work has addressed this problem in advanced packages, which involves complex routing rules and increased congestion, resulting in high computation cost. In this thesis, we propose a novel solution for the delay-matching problem in advanced packages by integrating commonly used patterns—accordion, trombone, and sawtooth—with a gridless routing. These popular patterns are used to adjust trace lengths while maintaining signal integrity. Our approach incorporates delay-matching awareness during the global routing stage to alleviate congestion in dense routing groups. In post-detailed routing, we utilize a sliding window-based method to detect DRV-free regions for detouring and propose a redistributed method to avoid congestion in parallel bus routing. Lastly, we develop a shape-based pattern routing method to obtain the routing result and fine-tune acute-angle wires for better manufacturability. Experimental results demonstrate the robustness and effectiveness of our proposed algorithm. Our approach is workable for PCB as well.

[1] W.-H. Liu, B. Chen, H.-Y. Chang, G. Lin, and Z.-S. Lin, “Challenges for automating package routing,” in Proceedings of the 2022 International Symposium on Physical Design, ISPD ’22, (New York, NY, USA), p. 193–194, Association for Computing Machinery, 2022.
[2] Z. Peterson, “Length matching for high-speed signals: Trombone, accordion, and sawtooth tuning,” https://resources.altium.com/p/length-matching-high-speedsignals-trombone-accordion-and-sawtooth-tuning, 2019.
[3] M. M. Ozdal and M. D. F. Wong, “A length-matching routing algorithm for highperformance printed circuit boards,” Trans. Comp.-Aided Des. Integ. Cir. Sys., vol. 25, p. 2784–2794, dec 2006.
[4] M. Ozdal and M. Wong, “Algorithmic study of single-layer bus routing for highspeed boards,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 3, pp. 490–503, 2006.
[5] J.-T. Yan and Z.-W. Chen, “Obstacle-aware length-matching bus routing,” in Proceedings of the 2011 International Symposium on Physical Design, ISPD ’11, (New York, NY, USA), p. 61–68, Association for Computing Machinery, 2011.
[6] Y. Kohira and A. Takahashi, “Cafe router: A fast connectivity aware multiple nets routing algorithm for routing grid with obstacles,” in Proceedings of the 2010 Asia and South Pacific Design Automation Conference, ASPDAC ’10, p. 281–286, IEEE Press, 2010.
[7] R. Zhang, T. Pan, L. Zhu, and T.Watanabe, “A length matching routing method for disordered pins in pcb design,” in The 20th Asia and South Pacific Design Automation Conference, pp. 402–407, 2015.
[8] T. Yan and M. D. F. Wong, “Bsg-route: A length-constrained routing scheme for general planar topology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 11, pp. 1679–1690, 2009.
[9] S.-T. Lin, H.-H. Wang, C.-Y. Kuo, Y. Chen, and Y.-L. Li, “A complete pcb routing methodology with concurrent hierarchical routing,” in 2021 58th ACM/IEEE Design Automation Conference (DAC), pp. 1141–1146, 2021.
[10] M. Lian, Y. Zhang, M. Li, T.-M. Tseng, and U. Schlichtmann, “Fxt-route: Efficient high-performance pcb routing with crosstalk reduction using spiral delay lines,” in Proceedings of the 2023 International Symposium on Physical Design, ISPD ’23, (New York, NY, USA), p. 53–61, Association for Computing Machinery, 2023.
[11] R.-B. Wu and F.-L. Chao, “Flat spiral delay line design with minimum crosstalk penalty,” IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, vol. 19, no. 2, pp. 397–402, 1996.