記憶體一直以來被認為是CMOS技術的主要驅動力之一，由於其高密度、大容量、關鍵時序及靈敏度等特性，因此記憶體診斷對技術和產品的開發是很重要。傳統上，記憶體錯誤樣型定義對記憶體診斷來說是一個很重要的任務，隨著記憶體的密度及容量不斷地成長，測試資料的數量也持續地增加，因此需要一個更有效率的錯誤樣型抽取方法。在本文中，我們提出了一個掃描線為基礎的記憶體錯誤樣型抽取器來加快抽取的過程。我們所提出的工具可以在大約35分鐘的時間，從20片業界上最先進的晶圓中抽取出記憶體錯誤樣型，跟目前最好的方法─以稀疏矩陣為基礎的方法來做比較，減少了15%的抽取時間。在我們的實驗中，我們也能從業界的產品裡發現一個以前沒有定義過的關鍵錯誤樣型，顯示了抽取器更健全地定義錯誤樣型的能力。

Memories have been considered as one of the major drivers of CMOS technology, due to their high density, high capacity, critical timing, sensitivity, etc. Memory diagnosis is therefore important for technology and product development. Memory failure pattern identification is traditionally an essential task for diagnosis. As memory density and capacity continue to grow, the amount of test data also keeps increasing, thus a more efficient failure pattern extraction method is required. In this thesis, we propose a sweep-line-based memory failure pattern extractor to speed up the extraction process. The proposed tool can extract memory failure patterns from an industrial case of 20 state-of-the-art wafers in about 35 minutes, reducing 15% analysis time as compared with the sparse-matrix-based method that is the best so far. In our experiments of the industrial case, we are also able to identify a critical failure pattern that was not defined before, showing its more robust pattern identification capability.

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