本論文共分成四部份，首先此論文第一部份為三向閘極複晶矽多奈米線通道雙電晶體非揮發性記憶體(twin-TFT NVM)元件。過去本團隊製作雙電晶體非揮發性記憶體，結構為兩晶體共用相同浮停閘極，用較大尺寸電晶體當閘極，利用電壓偶合控制較小尺寸之電晶體，浮停閘極可儲存電荷並改變電晶體臨界電壓(Vth)。然而由於穿隧氧化層與阻絕氧化層為同一層，因此兩者厚度相同，再加上使用複晶矽為儲存層，因此在此提出兩種改善方式。第一種改善方式是將雙電晶體非揮發性記憶體元件做電漿處裡，薄膜電晶體可使用短時間之電漿鈍化修補通道與氧化層之缺陷，多項研究指出其開關特性可大幅改善。實驗結果呈現電晶體開關特性(次臨界斜率、載子遷移率、開關電流比)之改善，此外經氨電漿鈍化之記憶體寫抹速度及可靠度皆改善，並有改善機制之探討；第二種改善方式，我們將單層二氧化矽(SiO2)閘極氧化層改成二氧化矽(SiO2)/氮化矽(Si3N4)(簡稱O/N結構)。由於氮化矽的介電係數比二氧化矽高，因此在穿隧區之二氧化矽電場被增強；此外，由於氮化矽具有離散缺陷儲存之能力，因此即使有漏電路徑產生，儲存之電荷不會完全流失。使用O/N結構有效提高寫抹速度及可靠度。 最後我們提出一種可低溫製程的雙複晶矽電晶體非揮發性記憶體以InGaZnOx (IGZO) 作為儲存層，IGZO層可以於室溫下沉積。我們操作出5V以上的記憶窗，並且有好的可靠度。元件尺寸對記憶窗大小之影響在此作深入討論。
第二部份為應用金屬閘極(TaN)與高介電係數(Al2O3)之非揮發性記憶體元件，首先是具多條複晶矽奈米線通道TANOS非揮發性記憶體。氧化鋁具有比二氧化矽高的介電係數，且其對電子與電洞之能障高，很適合當作閘極氧化層；然而使用n型重摻雜之多晶矽閘極，在抹除時會造成不必要的閘極注入，導致臨界電壓變化之飽和；使用高功函數氮化鉭(TaN)閘極能有效抑制抹除時的閘極注入。在此我們結合TANOS及多條複晶矽奈米線通道。我們利用奈米線形成Pi型閘極結構，有效控制奈米線四個角落，因此有效利用尖端幫助寫抹，由實驗資料可知寫抹速度大幅提升。然而十年後電荷保存量剩原本之60%，因此還有改善的空間。我們引進矽奈米點(Si-NCs)來改善資料保久度，由於矽奈米點為離散程度高，介面有很多缺陷可提供儲存電荷，再加上矽奈米點可使儲存之電荷位於比氮化矽缺陷深的能態，因此矽奈米點更能防止漏電；此外矽奈米點為前段製程，對製程較無污染。由實驗數據可知，使用矽奈米點之TANOS非揮發性記憶體表現出極佳的可靠度。接著我們使用TANOS非揮發性記憶體作二位元操作，並且提供新的二位元操作模式。
第三部份我們結合環繞式閘極結構(Gate-all-around, GAA)與矽奈米點(Si-NCs)之非揮發性記憶體。環繞式閘極將奈米線通道包住，具有最佳的通道控制能力。除了環繞式閘極結構導致寫抹速度更提升，奈米點也有提高記憶窗的效果。使用奈米點之記憶體元件表現好的可靠度。由於矽奈米點亦具有離散缺陷儲存特性，此短通道元件亦可使用二位元操作。
第四部份我們結合多條複晶矽奈米線元件、SONOS結構、以及穿隧電晶體(TFET)。由於穿隧電晶體具有打破室溫下60 mV/dec.的限制，用於記憶體元件，有助於提高”0”與”1”狀態的判讀。穿隧電晶體元件為未來低靜態功率消耗之元件的解決方案之一。利用三向閘極結構能有助於穿隧電晶體的源極穿隧，有助於提高穿隧電流以及降低次臨界斜率。以此概念出發，我們SONOS結構之穿隧式非揮發性記憶體元件，具有大的記憶窗及優秀的可靠度。

This thesis is divided into four parts to demonstrate 3D IC applicable nonvolatile memories with nanostructures. In the first part, we improves the performance and reliability of a trigate polycrystalline silicon (poly-Si) nanowires twin-TFT nonvolatile memory (NVM) by NH3 plasma passivation and O/N structure. Trigate structure significantly enhances the programming and erasing speed, but a FG NVM device can not endure cycling stress. NH3 plasma contains H and N radicals. H radicals can passivate the grain boundaries in poly-Si channel and the interface trap at Si/SiO2 interface; N radicals can be combined with Si dangling bonds at the interface to form the Si-N bands, which are stronger than Si-H bonds. After NH3 plasma passivation, the TFT performs high Ion/Ioff and steep SS; passivated twin-TFT NVM shows larger memory window and improved endurance and retention. Secondly, we use O/N structure is to replace a single SiO2 layer. Nitride film has discrete charge trapping property; only a portion of the stored charge leaks out as a stress-induced leakage path (SILP) is formed. O/N structure enhances the electric field in tunneling dielectric, so an O/N structure twin-TFT NVM shows faster programming and erasing speed than an O/structure twin-TFT NVM. Thanks to the discrete charge trapping property, an O/N structure twin-TFT NVM shows good reliability. At last, a twin-TFT NVM with InGaZnOx (IGZO) FG is demonstrated. This NVM device with a low fabrication temperature is feasible for display application. An IGZO FG NVM exhibits large memory window and good retention.
In the second part, we study a pi-gate poly-Si NWs TANOS NVM. Pi-gate enhances the programming and erasing speed because corners induce higher electric field. Al2O3 has higher dielectric constant than SiO2, so TANOS can have higher αG than that of a SONOS NVM with the same blocking oxide thickness. Because TANOS NVM uses nitride CTL, it can be performed as 2 bits per cell. A kind of 2-bit operation based on F-N tunneling is demonstrated for a long channel TANOS NVM.
In order to obtain high-k Al2O3, high temperature annealing is necessary. However, high temperature causes Al2O3 to be crystallized. The grain boundaries of the Al2O3 behave as leakage paths that the stored charge in nitride can leak to gate through those grain boundaries. Introducing nanocrystals (NCs) in NVM devices was reported to improve retention. We introduce Si-NCs in TANOS NVM for improving the retention.
In the third part, we demonstrate a gate-all-around (GAA) structure SONOS NVM with Si-NCs charge trapping layer. GAA structure has the best gate control in multi-gate structure. GAA structure concentrates the electric field in tunneling oxide, and lessens that in blocking oxide. NCs reduce the charge loss and possess discrete charge trapping property. GAA NCs NVM shows fast programming and erasing speed, good reliability and can perform 2-bit operation.
Finally, a trigate NWs TFET SONOS (T-SONOS) NVM is demonstrated. First, we introduce the trigate structure to improve the performance of a TFET. The Ion, Ion/Ioff and SS can be significantly improved by trigate. Furthermore, corners of trigate enhance the electric field for F-N tunneling. This proposed T-SONOS performs large memory window and good reliability.

Chapter 1
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Chapter 3
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Chapter 5
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Chapter 6
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