奈米級金屬-氧化物-半導體場效電晶體閘極漏電流與等效長度鑑析

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研究生：	葉俊佳 Chun-Chia Yeh
論文名稱：	奈米級金屬-氧化物-半導體場效電晶體閘極漏電流與等效長度鑑析 Characterization of Gate Leakage Current and Channel Length of Nanometer-scaled MOSFETs
指導教授：	龔正 J. Gong
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2007
畢業學年度：	96
語文別：	英文
論文頁數：	104
中文關鍵詞：	閘極漏電流、源極/汲極延伸區、等效長度
外文關鍵詞：	gate leakage current, SDE, effective channel length
相關次數：	點閱：3 下載：0
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本論文的研究是65奈米金氧半場效電晶體(MOSFET)直流特性的分析，內容包含兩大部分：閘極漏電流分析模型的建立以及源-汲極電流-電壓特性參數的萃取。

在閘極漏電流的分析中利用一組(bin)長寬組合內某些量測到的閘極漏電流 (IG)加上一個簡單的數學運算方法，可以找出漏電流的模型參數。利用這一組參數，可以準確預估這一組長寬範圍內其他長寬比電晶體的閘極漏電流。在此運算中考慮了淺溝渠隔離區 (STI)和源極/汲極延伸區 (SDE)對閘極漏電流的影響。在模擬的過程中只需要3個參數，而且不必理會會造成嚴重困擾的有效長度 (Leff)與有效寬度 (Weff)等問題。在本實驗中，我們驗證了此方法對於90奈米與65奈米元件的準確度，同時，我們也針對這3個參數受溫度的影響做了研究。由最後的結果來看，此方法可以準確、有效的估算出閘極漏電流在不同尺寸電晶體內隨偏壓與溫度的變化。

在源-汲極電流-電壓特性參數萃取方面，本論文採用了shift-and ratio (S&R)的觀念來計算等效通道長度(Leff)和源極/汲極電阻(RSD)。根據S&R的理論基礎，我們在計算等效通道長度和源極/汲極電阻時，修正了下面列出的效應：1. 還原閘極漏電流過大時的汲極電流，2. 速度飽和模型， 3. 擴散電流對於汲極電流的影響。將上述因素納入考慮後，我們可以推導出和Leff及RSD相關的8個非線性方程式。透過這些方程式的疊代計算去得到Leff和RSD隨VGS而改變的函數。擴散電流對65奈米元件特性的影響在本論文內會有深入且詳細的分析。

This dissertation contains the DC characterization of nanometer-scaled metal-oxide-semiconductor field-effect-transistors. Two major achievements are obtained: the establishment of a gate leakage current model and accurate parameter extraction from the drain to source current-voltage relations.

In first achievement, a mathematical method of modeling the gate leakage current IG is presented. Both the shallow trench isolation effect and the source drain extension effect on IG are included. With suitably chosen transistor dimensions the parameter extraction can be performed with the devices’ drawn size, the troublesome effective device length and width is not necessary in this model. The extracted parameters were used to predict IG of devices with other different dimensions. Transistors fabricated with 90nm and 65nm technologies were examined. The extracted parameters and their temperature dependence were used to predict IG of devices with other dimensions, excellent accuracy is verified.

In second achievement, the concepts of shift-and-ratio (S&R) method are used. According to this foundation, we point out some different viewpoints that include a drain current corrected by gate leakage current, surface potential, velocity saturation model, and diffusion current portion of the drain current. After considering these factors which relate to the effective channel length (Leff) and source/drain series resistance (RSD) and we can get eight nonlinear equations. Then, iteration method is applied to solve these equations to obtain accurate RSD and Leff. Because RSD and Leff are two inseparable device parameters, therefore, the iterated steps can obtain more accurate parameters simultaneously. The results differ from that obtained from the original S&R method; both our outcomes are function of VGS. Furthermore, our algorithm only needs to measurement IDS-VGS curve before calculating the results. Therefore, this proposed method can be easily implemented in MOSFET’s modeling.

Chapter 1 Introduction     1

Chapter 2 Mechanisms and Model of Leakage Current in Scaled Devices          5
1Subthreshold Leakage                                                       5
2 pn junction reverse-biased current                                          7
3 Punchthrough current                                                 8
4 Gate-induced drain leakage (GIDL) current                                9
5 Hot carrier injection current                                           10
6 Gate leakage current                                                 10
6.1 Gate direct tunneling current                                      11
6.2 Direct Tunneling                                               11
6.2.1 Mechanisms of direct tunneling                             12
6.2.2 Components of tunneling current                            12
7 Gate edge direct tunneling (EDT) current                                13
8 Summary                                                          14

Chapter 3 Gate Current Extraction
1 Experiments                                                       19
2 Results and Discussion                                              22
2 .1 Effect of VDS on gate leakage current modeling                         25
2 .2 Effect of VBS on gate leakage current modeling                         27
3 Temperature effect of parameters                                          28
4 Conclusions                                                       30

Chapter 4 The Extraction of the Effective Channel Length and Series Resistance
of a 65 nm Metal-Oxide-Semiconductor Field-Effect-Transistor
1 Introduction                                                        59
2 Review of Shift-and-Ratio (S&R) Method                                59
3 Using De La Moneda Method to extract                                  61
4 Correcting drain current ( )                                            62
5 Velocity Saturation Model                                            66
6 Extraction algorithm                                                    67
7 Results and discussions                                              71
8 Conclusions                                                        74

Chapter 5 Conclusion                                                    87

Reference                                                            89

                                

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Published papers

1. Chun-Chia Yeh, Chun-Feng Neih, Yen-Yu Chen, and Jeng Gong, “Simple and Accurate Method of Modeling Gate Current of N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor,” Jpn, J. Appl. Phys. vol. 46, No. 8A, 2007, p. 5133.
2. Chun-Chia Yeh, Chun-Feng Neih, Yen-Yu Chen, and Jeng Gong, “The Extraction of the Effective Channel Length and Series Resistance of a 65 nm Metal-Oxide-Semiconductor Field-Effect Transistor,” accept by Electronics Letters in 2007.
3. Chun-Chia Yeh, Chun-Feng Neih, Yen-Yu Chen, and Jeng Gong, “Temperature Effect of Metal-Oxide-Semiconductor Field-Effect-Transistors' Gate Current Evaluated with the Mask Dimensions,” accept by Solid State Electronics in 2007.
4. Chun-Chia Yeh, Chun-Feng Neih, Yen-Yu Chen, and Jeng Gong, “Modeling the MOSFETs' Gate Current with the Drawn Dimensions,” IEEE 2006 8th International Conference on Solid-State3 and Integrated Circuit Technology Electronic Version Proceedings, 2006, p. 1287

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