根據摩爾定律(Moore’s law)，在IC晶片上可容納的電晶體數目每隔18~24個月會加倍。因此，為了達到高運算速度與單位面積下高元件密度的目標，半導體工業不斷地將MOSFET的尺寸微縮。然而，元件尺寸的微縮即將面臨到蝕刻技術的極限。而由於一維半導體奈米結構在奈米電子與光電元件應用上有極大的潛力，因此成長一維半導體奈米結構的方式在近幾年來引起廣泛的研究。
首先，為了避免金屬觸媒的污染，我們以OAG的成長機制來成長矽奈米線，而且我們發現以此方式成長矽奈米線有兩個重要的成長條件：(1) 溫度梯度；(2) 成長環境須為負壓。由TEM的結構分析可知矽奈米線為核殼狀結構，其中核心為單晶的Si而周圍包覆著一層非晶質的氧化矽。為了成長可以調控尺寸的矽奈米線，我們試著找出矽奈米線的直徑與製程參數間的關係。在固定載送氣體流量的條件下，所合成的矽奈米線平均直徑隨著壓力增加而增加，而矽奈米線的密度則是隨著壓力增加而減少。當我們固定環境壓力時，可以發現矽奈米線的平均直徑會隨著載送氣體流量的增加而增加。另外，我們也發現矽奈米線傾向於在裂痕或缺陷這些能量較不穩定的區域生成。
當我們降低SiO粉末的溫度為1050℃，同時也將鍍金基板的溫度降低為620℃的情況下，我們所合成的奈米線成分為純Ge。這些Ge奈米線為核殼狀結構，其中核心為單晶的Ge，周圍則包覆著一層非晶質的GeOx。同時我們也發現Ge奈米線的直徑也隨著環境壓力增加而增加。
最後我們藉由在氧化鋁管中添加片狀碘的方式，我們成功地透過將SiO與Ge的粉末加熱，以熱蒸鍍的方式合成出Si1-xGex奈米線。此方法不具毒性、成本低廉，且ㄧ次在矽基板上就可以生成大量的Si1-xGex奈米線。在本論文中我們也提出了此方法的成長機制。合成出來的Si1-xGex奈米線為單晶且沿著[110]方向成長。

According to Moore’s law, the number of transitors on a computer chip would double every 18~24 months. Therefore, in order to achieve the goals of high operation speed and high device density, semiconductor industrials keep downscaling the size of MOSFETs. However, the reduction of device size would approach the limit of top down technology, therefore the method of synthesis one-dimensional (1D) semiconductor nanostructures is of particular interest because of their potential applications in nanoscale electronic and optoelectronic devices.
First, in order to grow Si nanowires without the contamination of gold catalysts, we used the method of OAG mechanism and we found two critical growth factors : (1) temperature gradient and (2) a pressure smaller than 1 atomosphere. From investigation of TEM images, we found the Si nanowire is core-shell structure with single crystalline Si core and amorphous silicon oxide shell. On the purpose of growing Si nanowires with controllable dimensions, we tried to find the relationship between the process parameters and nanowire’s diameters. At the same carrier gas flow rate, the average diameter of Si nanowires increases with the ambient pressure and the density of Si nanowires decreases with the ambient pressure. When we fixed the ambient pressure, we found that the average diameter of Si nanowires increases with the flow rate of carrier gas. We also discovered that the Si nanowires prefer to nucleate at the sites of cracks or defects first, which are energetically unstable.
When we decreased the temperature of SiO powder to 1050℃ and gold-coated Si substrate to 620℃, we could synthesize pure Ge nanowires. The Ge nanowire is core-shell structure with single crystalline Ge core and amorphous GeOx shell. The diameter of Ge nanowires increases with the ambient pressure as well.
Finally, by adding the iodine pellet(I2) into the alumina tube, we successfully synthesized the Si1-xGex nanowires by the method of simple thermal evaporation of SiO and Ge powder. This method is nontoxic、low cost and it can synthesize large amount of Si1-xGex nanowires on Si substrate at a time. In this thesis, we proposed the growth mechanism as well. The Si1-xGex nanowire is single crystal and its growth direction is [110] with Ge ranging from 3.70% to 17.76%.

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