電晶體的尺寸隨著半導體技術的發展而縮減，這樣的縮減使得電路更加容易受到軟錯誤的影響，軟錯誤是指錯誤的信號或資料被儲存元件儲存記錄。因此，最近幾年減少軟錯誤率已成為一個重要的問題。在這篇論文中，我們提出兩種方法來盡量減少軟錯誤率基於一種電路重組技術，非冗餘的移除刪及添加。我們提出的第一種方法是將較高的軟錯誤率發生的邏輯閘做線路重置，而第二個方法是對較高的軟錯誤
影響的子電路做結構重組。實驗結果表明，使用ISCAS'85和MCNC的測試電路，第一種方法減少了19.6％的電路軟錯誤率和9.9％電路面積。第二種方法用增加了9.6％的電路面積去得到23.7％的電路軟錯誤率的減少。通過結合這些兩種方法，我們可將軟錯誤率降低率與面積增加率的比例提高至高達6.77。此比例表明我們的方法可以用小成本來減少軟錯誤率。

With the advances of semiconductor technology, the transistor size has been scaled down. This shrinkage makes the circuits more susceptible to the soft error, which is a wrong signal or data latched by storage elements. Thus, Soft Error Rate (SER) reduction has become an important issue recently. In this work, we propose two methods for minimizing this SER based on a circuit restructuring technique, IRredundancy Removal and Addition. Our first method is to rewire the higher SER gates while the second
one is to restructure the subcircuits having higher soft error impacts. Experiential results show that the first method presents a reduction of 19.6\% SER and 9.9\% area on a set of ISCAS'85 and MCNC benchmarks on average. The second method gets 23.7\% soft error rate reduction with 9.6\% area overhead. By combining these two methods, we can rise the ratio of SER decreasing rate to area increasing rate up to 6.77. This ratio indicates our approach can
reduce the SER within a small cost.

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