快速且正確的匯流排競爭分析 – 使用有限狀態機交易層級建模方法

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研究生：	利茂霖 Li, Mao-Lin
論文名稱：	快速且正確的匯流排競爭分析 – 使用有限狀態機交易層級建模方法 Fast and Accurate Contention Analysis Using an FSM - based TLM Bus Modeling Approach
指導教授：	蔡仁松 Tsay, Ren-Song
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2011
畢業學年度：	99
語文別：	英文
論文頁數：	49
中文關鍵詞：	匯流排
相關次數：	點閱：2 下載：0
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這篇論文提出了一個有效的時脈數精準的交易層級匯流排模型及模擬方法。利用有限狀態機為基礎的匯流排傳輸與仲裁元件複合模型，搭配所提出的動態模擬演算法來加速系統晶片開發流程，此套方法適用於多重處理器系統晶片的匯流排效率評估及競爭分析。實驗結果呈現本論文所提出的方法較傳統時脈精準的匯流排模型有二十三倍的速度提高，並保持正確的時脈資訊。

Contents

   Introduction
   Related Work
   Preliminary
1.    A Formal Communication Interface Model
   Generic TLM Bus Modeling
1. A Two-Phase Arbiter Model
2. A Formal Generic Bus Model
   The Proposed Approach
1. Static Model Abstraction
1.1 Master-slave pair model compression
1.2 The composite master-slave pair and arbiter transaction (CMSAT) model
2 Full-bus Dynamic Simulation
2.1 Managing request queue
2.2 Dynamic full-bus simulation Algorithm
3 Discussions
3.1 Bus Preemption
3.2 Early burst termination
   Experimental Results
1 PAC System
1.1 Accuracy
1.2 Performance
Conclusion
Bibliogphy

                                

[1] L. Cai, D. Gaski. “Transaction Level Modeling: An Overview,” in CODES+ISSS, Newport Beach, California, USA, October 2003
[2] T. Grotker, S.Laio, G. Martin, S. Swan, System Design with SystemC, Kluwer Academic Publishers, 2002.
[3] S. Pasricha, N. Dutt, M. Ben-Romdhane, “Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration,” in DAC, San Diego, California, USA, June 2004
[4] C. K. Lo, R. S. Tsay, “Automatic Generation of Cycle Accurate and Cycle Count Accurate Transaction Level Bus Models from a Formal Model,” in ASP-DAC, Yokohama, Japan, January 2009
[5] ARM Ltd. AMBA Protocol Specification. www.arm.com
[6] Open SystemC Initiative (OSCI). SystemC 2.2.0 Documentation. www.systemc.org
[7] M. Caldari, et al., “Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0” in DATE, Munich, Germany, March 2003
[8] Open Core Protocol International Partnership (OCP-IP). www.ocpip.org.
[9] Coware. www.synopsys.com
[10] V. D’silva, S. Ramesh, and A. Sowmya, “Synchronous Protocol Automata: A Framework for Modeling and Verification of SoC Communication Architecture”, Proc. Design Automation and Test in Europe, 2004, pp. 20-27
[11] M. Radetzki, R. Salimi Khaligh, “Modelling Alternatives for Cycle Approximate Bus TLMs,” in Proc. Forum on Design Languages(FDL), 2007
[12] Parallel Architecture Core, available on: Industrial Technology Research Institute (ITRI). http://www.itri.org.tw

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