Multiple-Core Testing Architecture for HOY Wireless Testing Platform

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研究生：	陳松裕 Chen, Sung-Yu
論文名稱：	Multiple-Core Testing Architecture for HOY Wireless Testing Platform 后羿無線測試平台之多受測電路測試架構
指導教授：	劉靖家 Liou, Jing-Jia
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	89
中文關鍵詞：	后羿系統、無線測試系統、多受測電路、測試架構
外文關鍵詞：	HOY System, Wireless Testing
相關次數：	點閱：4 下載：0
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In the recent years, difficulties in integrated circuits (IC) testing keep growing quickly due to
the rapid progress of sub-micron manufacturing processes and increasing complexity of large-scale
chips such as system-on-chip (SoC) systems. The HOY (Hypothesis, Odyssey, Yield) system has
brought a brand new methodology to IC testing that utilize wireless RF communication for data
transfer instead of probe cards of traditional ATEs. The wireless channel and the packet-based
data transfer greatly reduce the cost of testing. To unify the communication interface for various
test protocols, i.e. scan test, BIST, etc., a CUT-dependent (HOY) test wrapper is employed, which
bridges between test circuits and HOY communication modules. Yet, previous version of HOY
wrapper can only support one CUT at once that is apparently insufficient for an SoC chip consisting
of various types of test circuits.
In the thesis we propose an architecture to make the wrapper support multiple circuits-under
test (CUTs), named Multiple-Core Test Architecture for HOYWireless Testing Platform (MUCA).
To support multiple-CUTs, the Controller and the Slave has been introduced into the wrapper. The
two modules can be configured to enable a specific CUT for testing. A new test procedure has been
proposed to make use of the new wrapper. The hardware and the test procedure make the wrapper
able to test multiple CUTs.
Additionally, the wrapper is clearly partitioned into two portions: one is CUT-independent, and
the other is CUT-dependent. The partition greatly facilitates the automation of wrapper synthesis.
Besides, the CUT-independent portion of HOY wrapper can then be included into HOY communication
modules as a single hard-IP with a set of external slot for plugging CUTs. Therefore
designers can spend lesser cost and integration efforts to use the HOY system.
In order to reduce test time, test scheduling has been considered in this work. Once a CUTneeds long execution time for testing or diagnosis, the test controller would not lie idle. The wrapper
makes the CUT into the background and tests of other CUTs can be performed simulataneously.
Test results can be retrieved later when the test is finished.
Finally, automation is done too. By using a device-under-test (DUT) configuration file, a set
of core test language (CTL) files, and the register-transfer-level (RTL) codes of the circuits, the
automation program produces the HOY system ready files.
MUCA has been verified through test benches and test programs for different types of DUTs.
Moreover, a test chip using this architecture has been tape-out. Results shows that it provides the
functionality at low area overhead. For three-core cases, the area of the HOY Test Wrapper is
around 10K gates. Among different CUTs, The area of MUCA, growing linearly with respect to
CUT, is one to three percent of that of the HOY Test Wrapper. In a tape-out chip, the wrapper costs
12.8K gates, or 3.49% of the CUT.

近年來，由於積體電路製程快速進展，及大型晶片，如系統晶片(system-on-chip, SoC)日益複雜，其測試出現各種難題。后羿(Hypothesis, Odyssey, and Yield, HOY)系統利用無線射頻通訊進行資料傳輸，取代使用探針卡之傳統機台，為積體電路測試帶來嶄新方法。此無線頻道及其上之封包式資料傳輸，大量減低測試成本。為一統各種測試協定(scan test, BIST 等等)之傳輸介面，后羿測試封套隨著受測電路建立，作為測試電路及后羿傳輸模組之橋梁。但是，先前之后羿測試封套僅能一次測試一個電路，無法滿足系統晶片擁有各式測試電路之需求。本論文提出多受測電路測試架構(MUCA)，可使封套支援多受測電路。為此，封套加入控制器及受控制器，可選取特定受測電路以供測試。測試程序亦隨之翻新。此硬體及測試程式之組合使封套能支援多受測電路。此外，封套依據是否與受測電路相關分為兩部份，有利於自動合成。另外，封套中於受測電路無關的部份，可於併入通訊模組自成一矽智財，並提供擴充介面，可插入其他受測電路，因而減少使用后羿系統之成本及整合人力。為縮短測試時間，亦兼顧測試排程。即使受測電路之測試耗時，封套亦不閒置。封套使其背景執行，因而同時測試其他電路。測試完畢後結果可以取回。最後，也支援自動化。利用受測裝置描述檔，及電路之受測電路描述與程式碼，自動化程式生成后羿相關檔案。此架構已於各式受測電路，以硬體模擬及測試程式驗證。另外，已有使用此架構之測試晶片下線。結果顯示，MUCA僅增加少量額外面積。以三電路而言，封套面積約在 10K 邏輯閘。MUCA之面積與電路個數成正比，為全封套之百分之一至三。於一下線晶片，封套使用12.8K邏輯閘，占受測電路之3.49%。

Introduction 11
1 The Rising of SoC Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Packet-basedWireless Testing System and Wrapper Synthesis / Test Program Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Multiple CUT Testing Architecture and Automation . . . . . . . . . . . . . . . . . 12
4 Organization of This Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Previous and Related Works 15
1 HOY: the Wireless Testing Platform . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1 The Overall Structure of HOY . . . . . . . . . . . . . . . . . . . . . . . . 15
1.2 Upcoming Challenges of HOY . . . . . . . . . . . . . . . . . . . . . . . . 18
2 Core Test Language, HOY Extension, and Parser . . . . . . . . . . . . . . . . . . 19
2.1 Core Test Language (CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Major blocks of CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3 HOY Extension to CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 CTL Parser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.1 Program Concepts . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.2 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3
2.4.3 Design Decisions . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 HOY Test Wrapper Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1 New Wrapper Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2 Mapping of CTL blocks to Wrappers . . . . . . . . . . . . . . . . . . . . 28
3.3 FSM synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MUCA: Multiple-Core Testing Architecture for HOY Wireless Testing Platform 34
1 Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.1 Evolution of HOY Test Wrapper . . . . . . . . . . . . . . . . . . . . . . . 34
1.2 Introduction of the Controller and the Slave . . . . . . . . . . . . . . . . . 37
2 Revised Test Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3 Generic Instruction Fetch Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4 External Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1 Introduction of External Slots . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Splitting the HOY Test Wrapper . . . . . . . . . . . . . . . . . . . . . . . 48
4.3 The Interface of External Slots . . . . . . . . . . . . . . . . . . . . . . . . 51
5 Test Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.1 Where Test Scheduling Can Work . . . . . . . . . . . . . . . . . . . . . . 53
5.2 Conceptual Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3 Protocol inside the HOY Test Wrapper . . . . . . . . . . . . . . . . . . . 55
5.4 Hardware Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.5 Software Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4
Automation 59
1 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
1.1 Inputs of MUCA Automation . . . . . . . . . . . . . . . . . . . . . . . . 59
1.2 The Internals MUCA Automation . . . . . . . . . . . . . . . . . . . . . . 61
1.3 The Interaction with the Wrapper Compiler . . . . . . . . . . . . . . . . . 61
2 DUT Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.1 The general section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.2 The places section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.3 The dut section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.4 The cut sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3 Generation of HOY files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.1 The Retrieval of Codelets . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.2 Generation of MUCA-enabled files . . . . . . . . . . . . . . . . . . . . . 65
4 Cache for CTL Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5 Threading in MUCA Automation . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Experiments and Results 70
1 MUCA Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
1.1 Case I: MBISTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
1.2 Case II: A mixed case . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2 Comparison with STEAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.1 Detailed Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3 The Taped-out Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.1 Architecture of the Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.2 Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Conclusion 80
1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
A User guide 82
A.1 Using the MUCA Automation Program . . . . . . . . . . . . . . . . . . . . . . . 82
A.1.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
A.1.2 MUCA Automation in a Nut Shell . . . . . . . . . . . . . . . . . . . . . . 82
A.1.3 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
B References 87

                                

[1] J. Jahangiri, N. Mukherjee, W.-T. Cheng, S. Mahadevan, and R. Press, “Achieving High Test
Quality with Reduced Pin Count Testing,” Proceedings of IEEE Asia Test Symposium, pp.
312–317, Dec. 2005.
[2] V. Iyengar, K. Chakrabarty, and B. T. Murry, “Huffman Encoding of Test Sets for Sequential
Circuits,” IEEE Transactions on Instrumentation and Measurement, vol. 47, pp. 21–25, 1998.
[3] C.-W.Wu, C.-T. Huang, S.-Y. Huang, P.-C. Huang, T.-Y. Chang, and Y.-T. Hsing, “The HOY
Tester – Can IC Testing Go Wireless?” Proceedings of International Symposium on VLSI
Design, Automation and Test, 2006.
[4] P.-K. Chen, Y.-T. Hsing, and C.-W. Wu, “On Feasibility of HOY- A Wireless Test Methodology
for VLSI Chips and Wafers,” Proceedings of International Symposium on VLSI Design,
Automation and Test, 2006.
[5] J.-J. Liou, C.-T. Huang, C.-W.Wu, C.-C. Tien, C.-H.Wang, H.-P. Ma, Y.-Y. Chen, Y.-C. Hsu,
L.-M. Deng, C.-J. Chiu, Y.-W. Li, and C.-M. Chang, “A Prototype of a Wireless-based Test
System,” Proceedings of IEEE International SOC Conference, 2007.
[6] B. Moore, C. Sellathamby, P. Cauvet, H. Fleury, M. Paulson, M. Reja, L. Fu, B. Bai, E. Reid,
I. Filanovsky, and S. Slupsky, “High Throughput Non-contact SiP Testing,” Proceedings of
IEEE International Test Conference, 2007.
[7] C.-Y. Lo, C.-H. Wang, K.-L. Cheng, J.-R. Huang, C.-W. Wang, S.-M. Wang, and C.-W. Wu,
“Steac: A platform for automatic soc test integration,” Very Large Scale Integration (VLSI)
Systems, IEEE Transactions on, vol. 15, no. 5, pp. 541–545, May 2007.
[8] “IEEE Std. 1450.6-2005, IEEE Standard Test Interface Language(STIL) for Digital Test Vector
Data - Core Test Language(CTL),” IEEE Press, New York, 2005.
[9] L.-M. Denq and C.-W. Wu, “A Hybrid BIST Scheme for Multiple Heterogeneous Embedded
Memories,” Proceedings of IEEE Asia Test Symposium, 2007.
[10] H. C. Song, S. C. Liang, and H. C. Hong, “A cost effective BIST second-order S - D modulator,”
IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, 2008.
[11] C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, “A high-throughput low-cost AES processor,”
IEEE Communication Magazine, 2003.

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