完整編碼抗雜訊干擾反及閘型唯讀記憶體｜國立清華大學博碩士論文庫

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研究生：	梁志瑋 Liang, Chih-Wei
論文名稱：	完整編碼抗雜訊干擾反及閘型唯讀記憶體 The Full Code-pattern Coverage Noise Immunity NAND-type ROM
指導教授：	張孟凡 Chang, Meng-Fan
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	98
語文別：	英文
論文頁數：	114
中文關鍵詞：	串音干擾、反及閘型唯讀記憶體
外文關鍵詞：	Crosstalk, NAND-type ROM
相關次數：	點閱：2 下載：0
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NAND-type Read-Only-Memory (NAND-type ROM) is one of the nonvolatile memories and provides small size, low cost, large data storage capacity. The noise interference cause read failure, speed degradation and power consumption in NAND-type ROM. The dynamic source line charging is proposed to eliminate noises such as crosstalk effect, charge sharing and BL leakage in NAND-type ROM achieves full code pattern coverage. The gate leakage current can be suppressed with small area overhead in NAND-ROM cell array. The 256kb NAND-type ROM macro was implemented using 90nm logic process. Dynamic power and standby power can be reduced compare with conventional NAND-type ROM. The speed of proposed NAND-type ROM can improve 40.79%. The supply voltage of proposed scheme can be down to 0.31V.

目前很多可攜式的系統單晶片中，非揮發性記憶體被用於儲存系統程式和預存資料庫，為系統單晶片中的一部分。快閃記憶體有可靠度問題、需使用特殊記憶體製程，複雜度高，與先進製程有3~4代的製程差距。唯讀記憶體使用邏輯製程與其他製程相容性高，且唯一大儲存容量，小尺寸、低成本、低消耗功率，高速度操作的特性，是目前講求高速度的系統晶片不可或缺的基礎功能區塊。反及閘型唯讀記憶體的特點相較於反或閘型唯讀記憶體優點在於面積小、密度高、漏電流小，待機功率小，位元線上的負載與漏電流與碼無關，功率容易被預測。
因製程微縮，金屬線與金屬線之間的距離接近導致嚴重的串音干擾效應，探討在90奈米的製程之下解決位反及閘型唯讀記憶體位元線與位元線之間的雜訊干擾、電荷分享效應及位元線漏電流所導致讀取速度降低與讀取失敗。我們提出了動態源極充放電路可以消除傳統反及閘型唯讀記憶體所不能避免發生位元線與位元線之間的雜訊干擾，電荷分享效應與位元線漏電流影響，避免因為不同的儲存資料導致待機電流大幅度的變化，且不會造成延遲增加與短路電流的發生。
記憶體細胞陣列呈現的方式是以16個細胞為一個細胞串，每一個細胞串經由專屬的選擇電晶體連接到位元線，32個細胞串連接到位元線，512條位元線的細胞陣列完成16K×16的反及閘型細胞陣列來驗證位元線已消除雜訊干擾，使反及閘型唯讀記憶體讀取速度加快，操作功率消耗與待機功率降低且具有100%編碼覆蓋範圍與最低操作電壓可降至0.31V。

Contents
Abstract (Chinese)
Abstract (English)
Acknowlegments (Chinese)
Contents ............................................................................................................................ I
List of Figures ................................................................................................................. V
List of Tables .................................................................................................................. X
Chapter 1. Introduction ......................................................................................... - 1 -
1 Background .................................................................................................. - 1 -
2 Motivation .................................................................................................... - 2 -
3 Thesis Organization ..................................................................................... - 4 -
Chapter 2. Characteristic of NAND-ROM and NOR ROM .............................. - 5 -
1 NOR-type ROM Structure and Operation ................................................... - 5 -
2 NAND-type ROM Structure and Operation ................................................ - 7 -
3 Comparison of NAND-type ROM and NOR-type ROM ............................ - 9 -
4 ROM Macro Architecture and Operation .................................................. - 11 -
5 Cell Current of NAND-structure ............................................................... - 12 -
6 Leakage Current of NAND-type ROM ..................................................... - 15 -
7 Charge Sharing Phenomenon of NAND-type ROM ................................. - 19 -
7.1 Charge Sharing Induced Read “1” Failure ........................................ - 20 -
7.2 Analysis of charge sharing in NAND-type ROM .............................. - 21 -
7.3 Charge Sharing with Coupling by Adjacent Charge Sharing ............ - 22 -
Chapter 3. Crosstalk Issue in ROM ................................................................... - 26 -
1 Crosstalk Effects in VLSI .......................................................................... - 26 -
1.1 Coupling Capacitance ........................................................................ - 26 -
1.2 A phenomenon of Crosstalk .............................................................. - 27 -
1.3 Methods for Reducing Crosstalk ....................................................... - 29 -
2 Crosstalk in ROM ...................................................................................... - 30 -
II
2.1 Sensing Error ..................................................................................... - 33 -
2.2 Slow Down the Memory Read Speed ................................................ - 34 -
3 Previous Methods for Solving Crosstalk in Memory ................................ - 35 -
3.1 BL shielding for FLASH memory ..................................................... - 35 -
3.2 Dynamic Virtual Guardian Techniques for NOR-type ROM ............ - 36 -
3.3 Crosstalk Noise Suppression in DRAM ............................................ - 40 -
4 Crosstalk in NAND-type ROM ................................................................. - 40 -
4.1 Read the Worse Case of Data “0” in NAND ROM ........................... - 40 -
4.2 Read Cell “1” in NAND ROM .......................................................... - 41 -
4.3 Reference Voltage Determination ..................................................... - 42 -
5 Analysis of Aggressor in NAND-type ROM ............................................. - 43 -
5.1 Code-dependent Aggressive Source Noise ........................................ - 43 -
5.2 Analysis of Aggressor in NAND String Size .................................... - 47 -
6 Analysis of Crosstalk in NAND-type ROM .............................................. - 48 -
6.1 Code-dependent Crosstalk ................................................................. - 48 -
6.2 Monte-Carlo Simulation for Crosstalk Variation .............................. - 51 -
6.3 Crosstalk Analysis for NAND-string Size ......................................... - 53 -
7 Probability of Failure Code Pattern ........................................................... - 54 -
Chapter 4. Proposed Scheme .............................................................................. - 57 -
1 Improvement of Using Dynamic Source Line Charging ........................... - 59 -
2 The Operation of Proposed Scheme .......................................................... - 59 -
3 Schematic and Layout of Proposed Scheme .............................................. - 61 -
4 Dynamic Source Line Loading .................................................................. - 63 -
5 Analysis of Divided Source Line ............................................................... - 65 -
6 Characteristic of Proposed Scheme ........................................................... - 67 -
6.1 Crosstalk Prevention by Proposed Scheme ....................................... - 67 -
6.2 Dynamic Source Line with Pre-charge Decoding Scheme ................ - 69 -
6.3 Split 4 Source Lines ........................................................................... - 70 -
6.4 Gate/Sub-threshold Leakage Reduction ............................................ - 71 -
6.5 Charge Sharing Reduction ................................................................. - 72 -
Chapter 5. ROM Macro Implementation .......................................................... - 74 -
1 Macro Architecture .................................................................................... - 74 -
2 The Waveform of Proposed NAND-type ROM ........................................ - 76 -
3 Layout of ROM Macro .............................................................................. - 77 -
4 Test Chip .................................................................................................... - 79 -
Chapter 6. Comparison and Experimental Results .......................................... - 80 -
1 Aspect Ratio and Size Analysis ................................................................. - 80 -
2 NAND Cell Size Comparison .................................................................... - 81 -
2.1 Conventional and Proposed NAND-string Size ................................ - 81 -
2.2 Cell Size Analysis .............................................................................. - 82 -
3 Reduction of Noise .................................................................................... - 84 -
3.1 Crosstalk Reduction ........................................................................... - 84 -
3.2 Charge Sharing Reduction ................................................................. - 84 -
3.3 BL Leakage Reduction ...................................................................... - 85 -
3.4 Crosstalk and Charge Sharing Reduction .......................................... - 85 -
3.5 Crosstalk Charge Sharing and BL leakage Reduction ....................... - 86 -
4 Noise of Read Cell-1 in Conventional NAND-type ROM ........................ - 87 -
5 Speed Improvement ................................................................................... - 89 -
6 Standby Current Improvement ................................................................... - 94 -
7 Standby Power ........................................................................................... - 97 -
8 Power Improvement ................................................................................... - 98 -
9 VDD-min Improvement ............................................................................. - 98 -
10 Comparison of Proposed ROM and Other ROMs ..................................... - 99 -
Chapter 7. Measurement Results ..................................................................... - 100 -
1 Test Chip Photo ....................................................................................... - 101 -
2 Function Test ........................................................................................... - 101 -
3 Oscilloscope Measurement ...................................................................... - 102 -
4 Estimate IO Pad Delay ............................................................................. - 105 -
5 VDD-min ................................................................................................. - 106 -
6 Standby Power and Operation Power ...................................................... - 107 -
7 Speed Measurement ................................................................................. - 107 -
8 Shmoo Plot ............................................................................................... - 108 -
Chapter 8. Conclusion and Future Work ........................................................ - 111 -
1 Conclusion ............................................................................................... - 111 -
2 Future Work ............................................................................................. - 111 -
References ................................................................................................................ - 112 -

                                

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