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研究生: 藍偉庭
Wei-Ting Lan
論文名稱: 應用於無線通訊之閉迴路二進制頻移鍵控調變射頻發射器
A Closed-Loop Binary Frequency-Shift-Keying RF Transmitter for Wireless Applications
指導教授: 柏振球
Jenn-Chyou Bor
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 114
中文關鍵詞: 頻移鍵控射頻發射器數位控制振盪器鎖相迴路
外文關鍵詞: FSK, RF Transmitter, DCO, PLL
相關次數: 點閱:3下載:0
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  • 本篇論文的主題為設計一個完全數位控制之二進制頻移鍵控調變的射頻發射器電路,並且適用於頻率範圍落在2.4-GHz下之無線通訊傳輸應用產品上。有別於以往傳統經由類比的電壓訊號來控制振盪頻率的振盪器電路,改採用一個帶有三級之切換式電容陣列的數位式振盪頻率控制振盪器電路作為這個二進制頻移鍵控調變射頻發射器系統的主要核心部分。在此頻移鍵控調變射頻發射器電路系統中,有兩組數位控制的回授迴路系統來控制數位式頻率控制振盪器的輸出頻率,以實現二進制頻移鍵控調變的數位通訊傳送。在作二進制數位資料調變傳送之前,代表邏輯0與邏輯1的輸出頻率所需要的數位控制振盪器頻率控制碼由一組使用二元搜尋演算法的數位控制迴路來產生並儲存起來。在二進制數位資料作頻移鍵控調變並傳輸時,另一個數位控制的相位鎖定控制迴路啟動,以將因為長時間的操作之下導致的輸出頻率偏移量消除。整個發射器電路系統經過模擬後利用台灣積體電路公司的互補式金屬-氧化層-半導體0.18微米混合訊號製程來實現,整個晶片的面積大小為1.1 × 1.1平方微米。根據模擬後的結果,射頻發射器輸出的頻率範圍大約落在2.36 ~ 2.59 GHz之間,而相位雜訊的部分在偏離中心的載波頻率500 kHz位移處約在-110 dBc/Hz的雜訊程度附近。另外,在250-kHz的資料傳輸速率下,輸出的頻率平均誤差可小於100-kHz。整體功率消耗在1.8 V的電壓供應下約為13 mW。


    This thesis presents the design of a fully digital controlled binary frequency-shift- keying (BFSK) RF transmitter for 2.4 GHz wireless applications. Instead of traditional voltage controlled oscillator (VCO), a digitally controlled oscillator (DCO) with three switched-capacitor arrays adopts as a core of this RF transmitter. There are two digital feedback loops to control the DCO to perform the BFSK transmission. Before data transmitting, the DCO codes for both logic-1 and logic-0 frequencies are generated and stored by a binary-searching digital calibration loop. When data modulating and transmitting, another digital phase-locked loop (PLL) is enabled to cancel the frequency shift induces by long-time operation. The designed transmitter is implemented in TSMC 0.18 μm CMOS process, and the chip area is 1.1 × 1.1 mm2. According to the simulation results, the frequency tuning range is around 2.36 ~ 2.59 GHz. The phase noise is about -110 dBc/Hz at 500 kHz offset frequency. For 250-kHz data-rate transmission, the frequency error is less than 100 kHz. The total power consumption is around 13 mW under 1.8 V power supply.

    Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 2 1.3 Thesis Organization 5 Chapter 2 Closed-Loop BFSK Transmitter Architecture 8 2.1 Introduction 8 2.2 BFSK Transmitter Design Specification 9 2.2.1 Output Frequency Range and Resolution 9 2.2.2 Frequency Accuracy 11 2.2.3 Phase Noise 12 2.2.4 Loop Bandwidth and Stability 13 2.3 Proposed BFSK Transmitter Architecture 14 2.3.1 Digitally Controlled Oscillator 15 2.3.2 Gated Edge Counter 17 2.3.3 Digital Frequency and Phase Control Loops 18 2.4 Transmitter Design Concepts 19 2.4.1 Frequency Generation for Transmitted Data 19 2.4.2 Frequency Calibration for Long-Time Shift 21 2.4.3 Transmitter Timing Control 22 2.5 Summary 24 Chapter 3 DCO and Edge Counter Design 25 3.1 Digitally Controlled LC Oscillator 25 3.1.1 Fundamentals of LC Oscillator for RF Applications 25 3.1.2 Negative Resistance Circuit 34 3.1.3 Switched-Capacitor Array 37 3.1.4 Spiral Inductor 47 3.1.5 Output Buffer 50 3.1.6 Biased Circuit 51 3.1.7 Simulation Results 52 3.2 Gated Edge Counter 56 3.2.1 Input Pre-Amplifier 57 3.2.2 Current Mode Logic AND Gate 58 3.2.3 Current Mode Logic D Flip-Flop with Asynchronous Reset 59 3.2.4 Rail-to-Rail Output Buffers and Biased Circuit 60 3.2.5 Cell-Based Edge Counter 62 3.2.6 Simulation Results 63 3.3 Summary 65 Chapter 4 Digital Frequency and Phase Control Loop Design 66 4.1 Frequency Control Loop 66 4.1.1 Digital Frequency Detection 66 4.1.2 Binary Searching Mechanism 67 4.2 Phase Control Loop 71 4.2.1 Digital Phase Detector 71 4.2.2 Digital Loop Filter 74 4.3 Summary 84 Chapter 5 Transmitter Implementation and Measurement Results 86 5.1 Open-Loop BFSK Transmitter 86 5.1.1 Mixed-Mode and Post Simulation 87 5.1.2 Measurement Results 93 5.1.3 Measurement Discussion 104 5.2 Closed-Loop BFSK Transmitter 106 5.2.1 Mixed-Mode and Post Simulation 107 5.2.2 Measurement Setup 111 5.3 Summary 112 Chapter 6 Conclusion and Future Work 113 6.1 Conclusion 113 6.2 Future Work 114

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