無線晶圓測試的成本估計｜國立清華大學博碩士論文庫

簡易檢索 / 詳目顯示

回結果列表

研究生：	高赫聲 Ho-Sheng Kao
論文名稱：	無線晶圓測試的成本估計 Test Cost Estimation for Wireless Wafer Test
指導教授：	張慶元 Tsin-Yuan Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	52
中文關鍵詞：	無線、晶圓測試、成本估計
外文關鍵詞：	wireless, wafer test, cost estimation
相關次數：	點閱：3 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

在測試階段中，測試成本與測試精確度是必須考量的問題。但隨著製程技術迅速地進步，許多的晶片可以整合到同一顆系統晶片內，使得測試面臨極度的挑戰。因為晶片速度提昇太快，現在大部分的晶片在測試時都無法操作在工作頻率，這將增加與時間相關錯誤機率的發生。另外接腳的密度與數量增加使得探針卡製作的難度與成本顯著提高。
后羿(HOY)計劃觀念近幾年被提了出來，它主要是針對傳統測試產生的種種問題而提出改良。后羿(HOY)觀念使用無線通訊的技術，將測試信號經由無線的方式傳送到待測晶片進行測試，如此可解決逐漸增加的晶片接腳密度與縮小的接腳大小問題，另外測試頻率的提高、測試時間的縮短等等優點，使后羿無線測試觀念擁有極大地魅力。
本篇論文以后羿(HOY)觀念為基礎修改前人所提出的成本模型，此模型是針對無內建自我測試電路的晶片所開發出的模型，它可以對三種測試方法進行評估，傳統測試方法、無辨識碼(ID)之無線測試方法與有辨識碼(ID)之無線測試方法。雖然說是使用無線測試，但只有輸入與輸出信號使用無線技術傳送資料，電源(clock)與時脈(clock)仍假設須經由探針卡來提供。經過評估之後，HOY無線測試方法可以大幅降低測試成本，又后羿(HOY)平行測試的個數比傳統測試多，所以測試一片晶圓花費的時間較少，單位時間內可測試的晶片較多，因此可獲得的利潤也較高。

Test cost and test accuracy are the issues that must be considered in the stage of testing. Many dies can be integrated into single chip with the advancement of integrated circuit fabrication technology, but it makes the testing face stern challenges. Because the speed of chip increases too fast such that some chips can not be tested at operation frequency, it will raise the possibility of time-related faults. The higher density and greater amount of pads make the manufacture of probe cards more difficult and more expensive than past.
HOY wireless test concept was proposed recently. It provides the improved test method due to plenty problems of traditional test. HOY concept is that test data are transmitted to DUT by using wireless communication technology. Therefore, the issues of pad density and pad size can be solved. Besides, the advantages such as improving test frequency and reduced test time etc. make the HOY wireless test attractive.
This thesis proposes the cost model by modifying the model in bibliography based on HOY concept. The proposed model is constructed for most of ASIC without BIST and it can estimate three types of test methods: traditional test, wireless test without ID, and wireless test with ID. Moreover, only the I/O signals are transmitted wirelessly and the power and clocks are still transmitted though the probe cards. After estimation, HOY wireless test method can save test cost enormously. In addition, the maximum number of parallel tests for wireless test is larger than that for traditional test, so the test time of wireless test is shorter than that of traditional test. That means that a wireless ATE can test more dies and obtain more profit.

Chapter 1    Introduction    1
Chapter 2    Previous Works    4
2.1    Wireless Test Technologies    4
2.1.1    Non-Contact Wafer Probe Using Wireless Probe Cards    4
2.1.2    Wireless Test Control Network With Radio-on-Chip
Technology    6
2.2    Cost Model    10
2.2.1    Traditional Cost Model    10
2.2.2    Wireless Cost Model for Embedded Memory Test    13
2.2.3    Test Time Model    16
2.3    Motivations    17
Chapter 3    Proposed Cost Model    18
3.1    Modified Traditional Cost Model    18
3.1.1    Test Cost Ctest_tr    18
3.1.2    Manufacture Cost Cmanu_tr    21
3.1.3    Operating Cost Cop_tr    21
3.2    Modified HOY Wireless Cost Model    21
3.2.1    Test Cost Ctest_hoy    22
3.2.2    Manufacture Cost Cmanu_hoy    26
3.2.3    Operating Cost Cop_hoy    26
3.2.4    Develop Effort Cost Ceffort    27
3.3    Test Time Model    28
3.3.1    Traditional Test Time Model    28
3.3.2    Wireless Test Time Model    29
Chapter 4    Simulation Results and Analysis    31
Chapter 5    Conclusions and Future Work    45
Appendix    47
Bibliography    49


List of Figures
    Figure 1.1:  ITRS 2003 roadmap [1]    2
    Figure 2.1:　Block diagram of non-contact wafer probe system [5]    5
    Figure 2.2:  Cross-sectional view of wafer probe system [5]    5
    Figure 2.3:  Block diagram of power transfer system [5]    6
    Figure 2.4:  Miniature wireless LAN architecture [6]    8
Figure 2.5:  Multihop architecture [6]    9
Figure 2.6:  Distributed multihop architecture [6]    10
Figure 2.7:  Traditional test time model [8]    16
Figure 2.8:  Wireless test time model [8]    17
Figure 3.1:  Wireless ATE for DUT without ID    23
Figure 3.2:  Wireless ATE for DUT with ID    24
Figure 3.3:  Traditional test time model    28
Figure 3.4:  Wireless test time model    29
    Figure 4.1:  The cost versus the number of parallel test sites    35
Figure 4.2:  Test time versus the number of parallel test sites    37
Figure 4.3:  The cost versus area overhead (α) for three types
of test methods (S= 1)    38
Figure 4.4:  The cost versus area overhead (α) for three types
of test methods (S= 20)    39
Figure 4.5:  The cost versus area overhead (α) for three types
of test methods (S= 40)    40
Figure 4.6:  The cost versus area overhead (α) for three types
of test methods (S= 40, Np=1)    41
Figure 4.7:  Total cost split for traditional test    42
Figure 4.8:  Total cost split for wireless test    43
Figure 4.9:  The benefit versus cost for traditional and wireless test    44


List of Tables

Table 4.1:          The impact on cost of traditional ATE with different
    numbers of parallel test sites    31
Table 4.2:      The impact on cost of wireless ATE without ID with
    different numbers of parallel test sites    32
Table 4.3:      The impact on cost of wireless ATE with ID with different
    numbers of parallel test sites    32
Table 4.4:      Cross comparison for traditional and wireless test methods
    (S = 1)    33
Table 4.5:      Cross comparison for traditional and wireless test methods
    (S = 20)    34
Table 4.6:      Cross comparison for traditional and wireless test methods
    (S = 40)    34
Table 4.7:      Test time analysis    36
Table 4.8:      The cost with difference area overhead (S = 1)    38
Table 4.9:      The cost with difference area overhead (S = 20)    39
Table 4.10:  The cost with difference area overhead (S = 40)    40
    Table A.1:      Parameters assumption    47

                                

[1] Semiconductor Industry Association, International Technology Roadmap for Semiconductors (ITRS), 2003 Edition, 2003.
[2] M. Sato, N. Otsuka, O. Muto, M. Arai, S. Fukumoto, and etc.; “Low-power Board- mounted Reconfigurable Tester Based on HDL Descriptions,” Proc. of 5th Workshop on RTL and High Level Testing, Nov. 2004, pp. 137-142.
[3] F. Pang, T. Brandon, B. Cockburn, and M. Hume, "A reconfigurable digital IC tester implemented using the ARM Integrator rapid prototyping system," Proc. of Canadian Conf. on Electrical and Computer Engineering, Vol. 4, May 2004, pp.1931-1935.
[4] R. Rajsuman, N. Masuda, and K. Yamashita, "Architecture and Design of an Open ATE to Incubate the development of Third-Party Instruments," IEEE Trans. On Instrumentation and Measurement, Vol.54, No.5, Oct. 2005, pp. 1678-1698.
[5] C.V. Sellathamby, M.M. Reja, L. Fu, B. Bai, and E. Reid, “Non- Contact Wafer Probe Using Wireless Probe Cards”, in Proc. International Test Conference, Nov. 2005.

[6] D. Zhao, S. Upadhyaya, and M. Margala, “ Design of a Wireless Test Control Network With Radio-on-Chip Technology for Nanometer System-on-a-Chip”, IEEE Trans. Comput.-Aided Des. Intergr. Circuits Syst., July 2006, pp. 1411 – 1418
[7] H. Eberle, A. Wander, and N. Gura, “Testing Systems Wirelessly”, in Proc. IEEE VLSI Test Symp., April 2004, pp. 335 – 340.
[8] P.-K. Chen, Y.-T. Hsing, and C.-W. Wu, “On Feasibility of HOY—A Wireless Test Methodology for VLSI Chips and Wafers”, in Proc. of International Symp. on VLSI DAT, April 2006, pp. 1 – 4
[9] B. Moore, M. Margala, and C. Backhouse, “Design of Wireless On-Wafer Submicron Characterization System”, IEEE Trans. Very Large Scale Integr. (VLSI) syst., Feb. 2005, pp. 169 – 180.
[10] J.-M. Lu and C.-W. Wu, “Cost and benefit models for logic and memory BIST”, in Proc. Design, Automation and Test in Europe (DATE), Paris, Mar. 2000, pp. 710–714.
[11] J. Rivoir, “Parallel test reduces cost of test more effectively than just a cheap tester”, in IEEE Electronics Manufacturing Technology Symposium, Montreal, July 2004, pp. 263–272.

[12] J. Rivoir, “Lowering cost of test: Parallel test or low-cost ate?”, in IEEE Asian Test Symp.(ATS), Xian, Nov. 2003, pp. 360–363.
[13] J. Khare, H. T. Heineken, and M. d’Abreu, “Cost trade-offs in system on chip designs”,Calcutta, Jan. 2000, pp. 178–184.
[14] J.-D. Lin, J.-M. Lu, and C.-W. Wu, “An improved VLSI test economics analysis system”, in Proc. 9th VLSI Design/CAD Symp., Nantou, Aug. 1998, pp. 149–152.
[15] J.-M. Lu and C.-W. Wu, “Cost and benefit models for logic and memory BIST”, in Proc. Design, Automation and Test in Europe (DATE), Paris, Mar. 2000, pp. 710–714.
[16] S. Wei, P.K. Nag, R.D. Blanton, A. Gattiker and W. Maly, “To DFT or not to DFT?”, in Proc. Int. Test Conf. (ITC), Nov. 1997, pp. 557–566.
[17] E.H. Volkerink, A. Khoche, L.A. Kamas, J. Rivoir and H.G. Kerkhoff, “Tackling test trade-offs from design, manufacturing to market using economic modeling” in Proc. Int. Test Conf. (ITC), Oct. 2001, pp.1098–1107.
[18] E.H. Volkerink, A. Khoche, J. Rivoir, and K.D. Hilliges, “Test economics for multi-cite test with modern cost reduction techniques”, in Proc. IEEE VLSI Test Symp. (VTS), Monterey, California, 2002, pp. 411–416.

[19] D. Zhao, S. Upadhyaya, and M. Margala, “A new SoC test architecture with RF/wireless connectivity” European Test Symp., May 2005, pp. 14–19.
[20] S. Bernard, D. Andreu, M.-L. Flottes, P. Cauvet, H. Fleury, and F. Verjus, “Testing system-in-package wirelessly” Int. Conf. on Design and Test of Integrated Systems in Nanoscale Technology, 2006, pp. 222–226
[21] B. Davis, “The Economics of Automatic Testing”, London, McGraw-Hill, 1994
[22] V. K. Kim, M. Tegethoff, and T. Chen, “ASIC yield estimation at early design cycle,” in Proc. Int. Test Conf. (ITC), Oct. 1996, pp. 590–594.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文