用於傳輸錯誤內建自我測試之最佳化線性反饋位移暫存器及種子轉換電路

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研究生：	邱顯仕 Sian-Shih Ciou
論文名稱：	用於傳輸錯誤內建自我測試之最佳化線性反饋位移暫存器及種子轉換電路 Optimization of LFSRs and Reseeding Logics for Transition Fault BIST
指導教授：	劉靖家 Jing-Jia Liou
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	45
中文關鍵詞：	內建自我測試電路
外文關鍵詞：	BIST
相關次數：	點閱：3 下載：0
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提出一個可以設計出高錯誤涵蓋率的線性反饋位移暫存器(Linear Feedback Shift Register, LFSR) 和種子轉換電路當作傳輸錯誤內建自我測試電路(Built-in Self Test, BIST)的測試樣本產生器。首先，我們用模擬降溫法( Simulated Annealing, SA)來搜尋出高品質的線性反饋位移暫存器然後利用我們提出的轉換種子方法來提高錯誤涵蓋率。在模擬降溫法過程中需要評估線性反饋位移暫存器很多次。所以我們發展出以機率為準的評估器和快速的錯誤模擬加入在模擬降溫法的架構中。如此一來，我們可以快速地選出一個高品質的線性反饋位移暫存器來偵測電路的傳輸錯誤。針對剩下來難以被測到的錯誤，將由特殊的自動樣本產生器(Automatic Test Pattern Generator, ATPG)來產生測試樣本。接著是從這些測試樣本中選出可以達到高錯誤涵蓋率的當作線性反饋位移暫存器的種子的搜尋方法。在我們的實驗結果中，我們所找出的線性反饋位移暫存器硬體架構在不增加多餘的面積的情況下可以多增加到3%的錯誤涵蓋率。同時我們所選的種子可以達到跟決定性的錯誤涵蓋率一樣高的值，但僅只使用到1.1%的決定性的測試樣本。

An algorithm is proposed to design high fault-coverage LFSRs and reseeding logic as a test pattern generator of a transition-fault BIST. First, we develop a simulated annealing (SA) algorithm to search a high-quality LFSR and then using our proposed reseeding method to increase the fault coverage. In our SA process, there are many times to estimate LFSRs. So we develop a process incorporating
a probability-based estimator and a fast fault simulation in simulated annealing framework. Therefore, we can select fastly one high-quality LFSR for detecting the transition faults of a circuit. For the remaining hard-to-detect faults, test patterns are generated with a specialized ATPG model. Another search process is then invoked to select high fault-coverage seeds for the LFSR from test patterns. The constructed hardware LFSR generator can increase the pseudo-random fault coverage as much as 3.26% without any additional overheads. Also the selected seeds can generate the same deterministic fault coverage with only 1.1% of the original test patterns.

Contents
Introduction 6
1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Problem Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Background 10
1 Delay Fault Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 Combinational Circuit Testing . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Transition Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 The Proposed BIST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Linear Feedback Shift Register (LFSR) . . . . . . . . . . . . . . . . . . . . . . . 14
5 Phase Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
The Proposed Method 16
1 Fault List Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1 Probability Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 fault list reduction method . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2 Restricted Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3 Probability-Based Transition Fault Simulation . . . . . . . . . . . . . . . . . . . . 23
4 Search Strategies for Initial Application Phase . . . . . . . . . . . . . . . . . . . . 24
5 Reseeding Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 Constrained ATPG with LFSR and Phase Shifter . . . . . . . . . . . . . . 28
5.2 Searching Algorithm for High-Coverage Seeds . . . . . . . . . . . . . . . 28
Experimental Results 30
1 Experiments on Fault List Reduction . . . . . . . . . . . . . . . . . . . . . . . . . 30
2 Experiments on Proposed Fault Simulation . . . . . . . . . . . . . . . . . . . . . 32
3 Experiments on Simulated Annealing . . . . . . . . . . . . . . . . . . . . . . . . 34
4 Experiments on Seeds Selection for Reseeding Phase . . . . . . . . . . . . . . . . 35
Conclusion and Future Work 40
1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

List of Tables
1 Percentage of agreement between our estimation and fault simulation on s9234 . . 24
2 Percentage of agreement between our estimation and fault simulation on s15850 . . 24
1 Experimental results on fault reductions . . . . . . . . . . . . . . . . . . . . . . . 32
2 The comparison of CPU time(s) of s9234 in different amounts of test patterns. . . . 33
3 The comparison of CPU time(s) of s15850 in different amounts of test patterns. . . 33
4 CPU time comparison of the restricted simulation, total fault simulation and
probability-based simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 Experimental results on Simulated Annealing search for high coverage LFSRs.
(inner loop criterion k = 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 Number of undetectable fault increases when taking phase shifters and LFSR into
account in ATPG (10k test patterns) . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 Experimental results on seeds selection method (10k test patterns) . . . . . . . . . 36
8 Experimental results on seeds selection method for 32-bits LFSR(100k test patterns) 37
9 The result of reseeding experiment for the different length of LFSR (10k test patterns) 37
10 Experimental results on seeds selection method for 64-bits LFSR(10k test patterns) 38
11 Experimental results on seeds selection method for 64-bits LFSR(100k test patterns) 38
12 The comparison of area overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

List of Figures
1 Testing scheme for combinational circuits . . . . . . . . . . . . . . . . . . . . . . 11
2 Transition Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 The proposed BIST architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Type-1 LFSR and Type-2 LFSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1 Random pattern resistant fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2 The overall flowchart for the proposed method . . . . . . . . . . . . . . . . . . . . 18
3 The flow chart of the probability simulation . . . . . . . . . . . . . . . . . . . . . 19
4 The calculation of a gate’s signal probability . . . . . . . . . . . . . . . . . . . . 20
5 The calculation of a gate’s observability . . . . . . . . . . . . . . . . . . . . . . . 21
6 Flowchart of SA algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 An Example of LFSR Encoding and XOR tree network . . . . . . . . . . . . . . . 26
8 Conceptual reseeding process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 Appending TPG circuitry into CUT to generate delay fault test patterns as seeds
for reseeding phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1 The calculation of a gate’s detection probability . . . . . . . . . . . . . . . . . . . 31
2 The calculation of a gate’s detection probability . . . . . . . . . . . . . . . . . . . 32

                                

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