深次微米積體電路製造技術的進步已推動著嵌入式記憶體(embedded
memory)的使用，並且對於系統單晶片(SOC)以及系統級封裝(SIP)而言，嵌入式非揮發性記憶體(embedded non-volatile memory)的強烈需求也使得快閃記憶體(flash memory)逐漸地越來越重要。此外，隨著嵌入式記憶體容量與面積的增長，系統單晶片的良率逐漸被嵌入式記憶體的良率所主宰。然而，記憶體中由深次微米缺陷以及製造參數不確定性所導致的良率損失一直是最重要的問題。為了解決此一問題，使用備用記憶體修復被認為是一個很有效率的方法來提升記憶體良率。對於嵌入式記憶體而言，自我修復系統(BISR)更是一個符合成本效益的解決方案。然而，在快閃記憶體上實作自我修復系統並非是微不足道的問題。

近幾年來，對於記憶體有許多有關於自我修復系統的研究成果提出，但是針對快閃記憶體而言，則尚未有適用的方法發表。在這篇論文中，我們針對NOR型與NAND 型快閃記憶體分別進行自我修復系統之探討與研究。自我修復系統包含了自我測試電路(BIST)、內建式備用記憶體分析電路(BIRA)以及晶片上修復電路(on-chip repair)。自我測試電路可以使用測試演算法來測試快閃記憶體，例如March FT。內建式備用記憶體分析電路可以分析錯誤之記憶體單元的資訊並找出修復方法，而晶片上修復電路可把錯誤單元以分配之備用記憶體置換。

對於NOR 型快閃記憶體上之自我修復系統，我們採用一個典型的備用記憶體架構，而基於這個架構，我們藉由著分析三個已知的備用記憶體分析演算法並提出一個方法。因為該典型的備用記憶體架構是一個有限制的二維行列備用記憶體架構，已知的演算法可能會發生錯誤修復的情形。因此，我們所提出的分析方法主要是一個貪婪演算法且高比重地使用備用行(spare row)，這個方法主要是基於前人所提出的ESP 演算法所發展而成。透過使用我們所提出的分析方法，錯誤修復的情形便可以避免。

對於NAND 型快閃記憶體而言，我們依據一個有效率的二維備用記憶體架構提出一個備用記憶體分析演算法，另外考慮到在NAND 型快閃記憶體中廣泛使用的頁面模式(page mode)操作所帶來的影響，我們也提出一個可以找到現在正在存取之位址的方法。由於在NAND 型快閃記憶體上特殊的記憶體單元排列，備用行的架構是不適用且不允許的，所以我們提出一種特殊備用記憶體單元，稱為備用NAND 型區塊(spare NAND block)。在此，我們修改ESP 演算法使其適用於該備用記憶體架構。然而，對於NAND 型快閃記憶體而言，晶片上修復電路是另一項問題。為了解決這個問題，自動產生現在正在存取之位址的方法是必須的。利用我們的方法，晶片上修復電路可以確切地知道正在存取的記憶體位址以進行修復。

我們也發展了一個模擬工具，而該工具支援NOR 型與NAND 型快閃記憶體。使用這個工具，我們模擬了提出來的方法。對於NOR 型快閃記憶體而言，模擬結果呈現出有缺陷的記憶體的確可以被有效地修復，而且結果也隱含著較偏好使用備用行的情形。另一方面，對於NAND 型快閃記憶體而言，結果呈現出備用NAND型區塊可能是比備用列(spare column)更好的選擇。

[1] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells—an overview”, Proc. of the IEEE, vol. 85, no. 8, pp. 1248–1271, Aug. 1997.

[2] IEEE, IEEE 1005 Standard Definitions and Characterization of FloatingGate Semiconductor Arrays, IEEE Standards Department, Piscataway, 1999.

[3] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancy analysis for memory yield improvement”, IEEE Trans. on Reliability, vol. 52, no. 4, pp. 386–399, Dec. 2003.

[4] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in selfrepair analyzer (CRESTA) for embedded DRAMs”, in Proc. Int’l Test Conf. (ITC), 2000, pp. 567–574.

[5] S.-Y. Kuo andW. K. Fuchs, “Efficient spare allocation in reconfigurable arrays”, IEEE Design & Test of Computers, vol. 4, no. 1, pp. 24–31, Feb. 1987.

[6] W.-K. Huang, Y.-N. Shen, and F. Lombardi, “New approaches for the repair of memories with redundancy by row/column deletion for yield enhancement”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 3, pp. 323–328, Mar. 1990.

[7] S.-K. Lu, Y.-C. Tsai, C.-H. Hsu, K.-H. Wang, and C.-W. Wu, “Efficient built-in redundancy analysis for embedded memories with 2-D redundancy”, IEEE Trans. on VLSI Systems, vol. 14, no. 1, pp. 34–42, Jan. 2006.

[8] Y. Nagura,M.Mullins, A. Sauvageau, Y. Fujiwara, K. Furue, R. Ohmura, T. Komoike, T. Okitaka, T. Tanizaki, K. Dosaka, K. Arimito, Y. Koda, and T. Tada, “Test cost reduction by at-speed BISR for embedded DRAMs”, in Proc. Int’l Test Conf. (ITC), Baltimore, Oct. 2001, pp. 182–187.

[9] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair design for RAMs with 2-D redundancy”, IEEE Trans. on VLSI Systems, vol. 13, no. 6, pp. 742–745, June 2005.

[10] P. Mazumder and J. S. Yih, “A novel built-in self-repair approach to VLSI memory yield enhancement”, in Proc. Int’l Test Conf. (ITC), 1990, pp. 833–841.

[11] P. Mazumder and Y.-S. Jih, “A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 1, pp. 124–136, Jan. 1993.

[12] T. Chen and G. Sunada, “Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips”, IEEE Trans. on VLSI Systems, vol. 1, no. 1, pp. 88–97, June 1993.

[13] D. K. Bhavsar, “An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264”, in Proc. Int’l Test Conf. (ITC), Atlantic City, Sept. 1999, pp. 311–318.

[14] V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words”, in Proc. Int’l Test Conf. (ITC), Baltimore, Oct. 2001, pp. 995–1001.

[15] S.-K. Lu and C.-H. Hsu, “Built-in self-repair for divided word line memory”, in Proc. IEEE Int’l Symp. on Circuits and Systems (ISCAS), 2001, pp. 13–16.

[16] M. Nicolaidis, N. Achouri, and S. Boutobza, “Dynamic data-bit memory built-in self-repair”, in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2003, pp. 588–594.

[17] M. Nicolaidis, N. Achouri, and L. Anghel, “A diversified memory built-in self-repair approach for nanotechnologies”, in Proc. IEEE VLSI Test Symp. (VTS), Napa Valley, Apr. 2004, pp. 313–318.

[18] C.-L. Su, R.-F. Huang, and C.-W. Wu, “A processor-based built-in self-repair design for embedded memories”, in Proc. 12th IEEE Asian Test Symp. (ATS), Xian, Nov. 2003, pp. 366–371.

[19] Y.-Y. Hsiao, C.-H. Chen, and C.-W. Wu, “A built-in self-repair scheme for NOR-type flash memory”, in Proc. IEEE VLSI Test Symp. (VTS), Berkeley, Apr. 2006, pp. 114–119.

[20] Y.-Y. Hsiao and C.-W. Wu, “A built-in self-repair scheme for NAND flash memory”, in Second IEEE Int’l Workshop on Design for Manufacturability and Yield (DFM&Y), Santa Clara, California, Oct. 2007.

[21] Y.-Y. Hsiao, C.-H. Chen, and C.-W. Wu, “Built-in self-repair schemes for flash memories”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Aug. 2010 (to appear).

[22] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories, Kluwer Academic Publishers, Boston, 1999.

[23] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to flash memory”, Proc. of the IEEE, vol. 91, no. 4, pp. 489–502, Apr. 2003.

[24] G. Campardo, M. Scotti, S. Scommegna, S. Pollara, and A. Silvagni, “An overview of flash architectural developments”, Proc. of the IEEE, vol. 91, no. 4, pp. 523–536, Apr. 2003.

[25] A. Silvagni, G. Fusillo, R. Ravasio, M. Picca, and S. Zanardi, “An overview of logic architecture inside flash memory devices”, Proc. of the IEEE, vol. 91, no. 4, pp. 569–580, Apr. 2003.

[26] I. Motta, G. Ragone, O. Khouri, G. Torelli, and R. Micheloni, “High-voltage management in single-supply CHE NOR-type flash memories”, Proc. of the IEEE, vol. 91, no. 4, pp. 554–568, Apr. 2003.

[27] Semiconductor Industry Association, “International technology roadmap for semiconductors (ITRS), 2007 edition”, Dec. 2007.

[28] M. G. Mohammad and K. K. Saluja, “Flash memory disturbances: Modeling and test”, in Proc. IEEE VLSI Test Symp. (VTS), Marina Del Rey, California, Apr. 2001, pp. 218 –224.

[29] J.-C. Yeh, K.-L. Cheng, Y.-F. Chou, and C.-W. Wu, “Flash memory testing and built-in selfdiagnosis with march-like test algorithms”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 6, pp. 1101–1113, June 2007.

[30] A. Chimenton, P. Pellati, and P. Olivo, “Overerase phenomena: An insight into flash memory reliability”, Proc. of the IEEE, vol. 91, no. 4, pp. 617–626, Apr. 2003.

[31] A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Chichester, England, 1991.

[32] J.-C. Yeh, C.-F. Wu, K.-L. Cheng, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, “Flash memory built-in self-test using march-like algorithms”, in Proc. IEEE Int’l Workshop on Electronic Design, Test, and Applications (DELTA), Christchurch, Jan. 2002, pp. 137–141.

[33] C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, “BRAINS: A BIST complier for embedded memories”, in Proc. IEEE Int’l Symp. on Defect and Fault
Tolerance in VLSI Systems (DFT), Yamanashi, Oct. 2000, pp. 299–307.

[34] M. Tarr, D. Boudreau, and R. Murphy, “Defect analysis system speeds test and repair of redundant memories”, Electronics, pp. 175–179, Jan. 12 1984.

[35] J. R. Day, “A fault-driven, comprehensive redundancy algorithm”, in IEEE Design & Test of Computers, June 1985, vol. 2, pp. 35–44.

[36] M.Mihara, T. Nakayama, M. Ohkawa, S. Kawai, Y.Miyawaki, Y. Terada, M. Ohi, H. Onoda, N. Ajika, M. Hatanaka, H. Miyoshi, and T. Yoshihara, “Row-redundancy scheme for highdensity flashmemory”, in Proc. IEEE Int’l Solid-State Cir. Conf. (ISSCC), 1994, pp. 150–151.

[37] H. Miwa, T. Tanaka, K. Oshima, Y. Nakamura, T. Ishii, A. Ohba, Y. Kouro, T. Furukawa, Y. Ikeda, O. Tsuchiya, R. Hori, and K. Miyazawa, “A 140mm2 64Mb AND flash memory with a 0.4μm technology”, in Proc. IEEE Int’l Solid-State Cir. Conf. (ISSCC), 1996, pp. 34–
35.

[38] G. Campardo, R.Micheloni, S. Commodardo, E. Yero,M. Zammattio, S.Mognoni, A. Sacco, M. Picca, A. Manstretta, M. Scotti, I. Motta, C. Golla, A. Pierin, R. Bez, A. Grossi, A. Modelli, A. Visconti, O. Khouri, and G. Torelli, “40-mm2 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory”, IEEE Jour. of Solid-State Circuits, vol. 35, no. 11, pp. 1655–1667, Nov. 2000.

[39] J. S. Park, “Multi-input/output repair method of NAND flash memory device and NAND flash memory device thereof”, U.S. Patent No. 7027330, Dec. 2002.

[40] T. Hara, K. Fukuda, K. Kanazawa, N. Shibata, K. Hosono, H. Maejima, M. Nakagawa, T. Abe, M. Kojima, M. Fujiu, Y. Takeuchi, K. Amemiya, M. Morooka, T. Kamei, H. Nasu, C.-M. Wang, K. Sakurai, N. Tokiwa, H. Waki, T. Maruyama, S. Yoshikawa, M. Higashitani, T. D. Pham, Y. Fong, and T. Watanabe, “A 146-mm2 8-Gb multi-level NAND flash memory with 70-nm CMOS technology”, IEEE Jour. of Solid-State Circuits, vol. 41, no. 1, pp. 161–169, Jan. 2006.

[41] T. Tanzawa, A. Umezawa, T. Taura, H. Shiga, T. Hara, Y. Takano, T. Miyaba, N. Tokiwa, K. Watanabe, H. Watanabe, K. Masuda, K. Naruke, H. Kato, and S. Atsumi, “A 44-mm2
four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller”, IEEE Jour. of Solid-State Circuits, vol. 37, no. 11, pp. 1485–1492, Nov. 2002.

[42] C.-T. Huang, J.-C. Yeh, Y.-Y. Shih, R.-F. Huang, and C.-W. Wu, “On test and diagnostics of flash memories”, in Proc. 13th IEEE Asian Test Symp. (ATS), Kenting, Taiwan, Nov. 2004, pp. 260–265.

[43] S.Matarress and L. Fasoli, “A method to calculate redundancy coverage for flash memories”, in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), San Jose, 2001, pp. 41–44.

[44] K.-J. Lin and C.-W. Wu, “Testing content-addressable memories using functional fault models and March-like algorithms”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 5, pp. 577–588, May 2000.

[45] J.-F. Li, R.-S. Tzeng, and C.-W. Wu, “Testing and diagnosis methodologies for embedded content addressable memories”, Jour. of Electronic Testing: Theory and Applications, vol. 19, no. 2, pp. 207–215, Apr. 2003.

[46] Y. Zorian and S. Shoukourian, “Embedded-memory test and repair: Infrastructure IP for SoC yield”, IEEE Design & Test of Computers, vol. 20, pp. 58–66, May-June 2003.

[47] Open NAND Flash Interface Workgroup, “Open NAND flash interface (ONFi) specification Rev2.0”, http://www.onfi.org/, 2008.

[48] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, “Raisin: Redundancy analysis algorithm simulation”, IEEE Design & Test of Computers, vol. 24, no. 4, pp. 386–396, Jul.-Aug. 2007.

[49] K.-T. Park, M. Kang, D. Kim, S.-W. Hwang, B. Y. Choi, Y.-T. Lee, C. Kim, and K. Kim, “A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories”, IEEE Jour. of Solid-State Circuits, vol. 43, no. 4, pp. 919–928, Apr. 2008.

[50] R.-A. Cernea, L. Pham, F. Moogat, S. Chan, B. Le, Y. Li, S. Tsao, T.-Y. Tseng, K. Nguyen, J. Li, J. Hu, J. H. Yuh, C. Hsu, F. Zhang, T. Kamei, H. Nasu, P. Kliza, K. Htoo, J. Lutze, Y. Dong,M. Higashitani, J. Yang, H.-S. Lin, V. Sakhamuri, A. Li, F. Pan, S. Yadala, S. Taigor, K. Pradhan, J. Lan, J. Chan, T. Abe, Y. Fukuda, H. Mukai, K. Kawakami, C. Liang, T. Ip, S.-F. Chang, J. Lakshmipathi, S. Huynh, D. Pantelakis, M. Mofidi, and K. Quader, “A 34 MB/s
MLC write throughput 16 Gb NAND with all bit line architecture on 56 nm technology”, IEEE Jour. of Solid-State Circuits, vol. 44, no. 1, pp. 186–194, Jan. 2009.

[51] R. Zeng, N. Chalagalla, D. Chu, D. Elmhurst, M. Goldman, C. Haid, A. Huq, T. Ichikawa, J. Jorgensen, O. Jungroth, N. Kajla, R. Kajley, K. Kawai, J. Kishimoto, A. Madraswala, T. Manabe, V. Mehta, M. Morooka, K. Nguyen, Y. Oikawa, B. Pathak, R. Rozman, T. Ryan, A. Sendrowski, W. Sheung, M. Szwarc, Y. Takashima, S. Tamada, T. Tanzawa, T. Tanaka, M. Taub, D. Udeshi, S. Yamada, and H. Yokoyama, “A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS”, in Proc. IEEE Int’l Solid-State Cir. Conf. (ISSCC), Feb. 2009, pp.
236–237.

[52] K. Takeuchi, T. Tanaka, and T. Tanzawa, “A multipage cell architecture for high-speed programming multilevel NAND flash memories”, IEEE Jour. of Solid-State Circuits, vol. 33, no. 8, pp. 1228–1238, Aug. 1998.

[53] K.-T. Park, M. Kang, S. Hwang, D. Kim, H. Cho, Y. Jeong, Y.-I. Seo, J. Jang, H.-S. Kim, Y.-T. Lee, S.-M. Jung, and C. Kim, “A fully performance compatible 45 nm 4-gigabit three dimensional double-stacked multi-level NAND flash memory with shared bit-line structure”, IEEE Jour. of Solid-State Circuits, vol. 44, no. 1, pp. 208–216, Jan. 2009.

[54] M. Saito, N. Miura, and T. Kuroda, “A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-die NAND-flash memory stacking”, in Proc. IEEE Int’l Solid-State Cir. Conf. (ISSCC), Feb. 2010, pp. 440–441.

[55] M. Saito, Y. Sugimori, Y. Kohama, Y. Yoshida, N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda, “2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking”, IEEE Jour. of Solid-State Circuits, vol. 45, no. 1, pp. 134–141, Jan. 2010.

[56] Y.-F. Chou, D.-M. Kwai, and C.-W.Wu, “Memory repair by die stacking with through silicon vias”, in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2009, pp. 53–58.