暫存器傳導階層向量挑選以實踐峰值功率模擬

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研究生：	楊青山 Ching-Shang Yang
論文名稱：	暫存器傳導階層向量挑選以實踐峰值功率模擬 RT-Level Vector Selection for Realistic Peak Power Simulation
指導教授：	黃錫瑜 Shi-Yu Huang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	95
語文別：	中文
論文頁數：	51
中文關鍵詞：	暫存器傳導階層、向量挑選、峰值功率模擬
外文關鍵詞：	RT-Level, vector selection, peak power simulation
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隨著半導體製程技術的演進，單位面積可容納的電晶體數目增加，除了促進可攜式電子產品的應用設計，另外所帶來的影響是功率消耗以非常驚人的速度增加，功率的問題也就逐漸嚴重。在功率的項目上，為了提高IC生產的良率，經常使用大量的輸入向量來模擬功率消耗的情形，藉以評估IC晶片生產的可行性；以目前市面上的輔助模擬軟體，必須花費大量的時間，同時也對系統造成沈重的負擔，才可以處理這些大量的輸入向量，對於IC設計的流程造成時間上的浪費。
過去的一些相關研究，可以歸納為以下三類：資訊理論方式，根據輸入與輸出的情形，考量訊號活動性與電容的因素，評估電路的功率消耗情形；資料庫模組方式，在較低的階層，如邏輯閘階層、電晶體階層，進行小型電路的測試與分析，根據小型電路的功率情形，建立功率消耗的資料庫，在暫存器傳導階層從輸入輸出訊號的變化，以數學式子評估功率消耗；或以自動向量產生器，採用一些峰值功率限制的方式，找出可能峰值功率的範圍。
在這本論文中，我們提出一個方法：在邏輯閘階層，透過電路的分析以及輸入向量模擬，對於每個輸入發生變動時所引發的功率波形特徵化為山形模型，應用簡單的數學運算方式，可以在暫存器傳導階層對這些工作輸入向量作篩選的動作，再將篩選過後的輸入向量透過輔助模擬軟體的模擬，可快速得到高準確度的峰值功率消耗。

We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with the accuracy of low-level power simulation. We rely on efficient RT-level peak power prediction heuristics to select a handful of input vector pairs from the simulation testbench. These vector pairs are highly likely to induce the worst-case peak power. After that, the low-level power simulation is performed only with these peak power candidate vector pairs to obtain the realistic peak power values. Computationally, there are three major stages in our methodology. Firstly, we analyze the structure of the circuit and calculate the peak power weight for each input pin so as to construct a so-called mountain-based model. Secondly, we perform waveform composition to compute the peak power metric for each given input vector pair. Finally, we select a few candidate vectors for low-level power simulation. By doing so, the time-consuming simulation at the low levels can be mostly avoided without losing accuracy. Experiment results show that only less than 1% of the total functional patterns defined in a testbench are needed to be selected for low-level power simulation in order to achieve 100% accuracy.

Contents
Abstract ……………………………………………………………… 01
Contents ……………………………………………………………… 02
List of Figures …………………………………………………… 04
List of Tables ……………………………………………………… 06
Chapter 1 Introduction …………………………………………… 07
1.1 Motivation ……………………………………………………… 08
1.2 Thesis Organization ………………………………………… 09
Chapter 2 Preliminaries ………………………………………… 10
2.1 Classification of Peak Power Estimation ……………… 10
2.2 Three Logic-Level Modeling Function …………………… 12
2.3 i-Max Algorithms ……………………………………………… 14
2.4 Mutually Exclusive Switching ……………………………… 16
Chapter 3 Proposed Methodology ………………………………… 19
3.1 Overall Methodology ………………………………………… 19
3.2 Mountain-Based Model ………………………………………… 20
3.3 Structure Analysis…………………………………………… 23
3.4 Peak Power Weight Calculation …………………………… 25
3.4.1 Simulation-Based Scheme ………………………………… 25
3.4.2 Structural Scheme ………………………………………… 27
3.5 Waveform Composition and Vector Selection …………… 28
Chapter 4 Implementation ………………………………………… 30
4.1 Implemental Flow ……………………………………………… 30
4.2 Circuit Characterization …………………………………… 32
4.3 Efficient Mountain Composition …………………………… 34
4.4 Vector Selection ……………………………………………… 36
4.5 Power Estimation ……………………………………………… 37
Chapter 5 Experimental Results………………………………… 39
5.1 Simulation Based Scheme …………………………………… 40
5.2 Structural Scheme …………………………………………… 43
5.3 CPU Time Comparison ………………………………………… 46
Chapter 6 Conclusion ……………………………………………… 49
Bibliography ………………………………………………………… 50


List of Figures
Fig. 2.1: Classification of peak power estimation …………12
Fig. 2.2: Gate delay and current model ………………………14
Fig. 2.3: An example of i-Max approach ……………………… 15
Fig. 2.4: A result of maximum envelope current ……………16
Fig. 2.5: Gate g5 and gate g11 have a conflict in delay-4 path ……………………… 17
Fig. 3.1: The overall flow of our methodology ………………20
Fig. 3.2: An example of explaining mountain ……………… 21
Fig. 3.3: Power contribution is like a mountain ………… 22
Fig. 3.4: A mountain-based model ……………………………… 23
Fig. 3.5: Example of structure analysis for input x5 …… 24
Fig. 3.6: An example to explain the contribution of an input …………………26
Fig. 3.7: Example of waveform composition ………………… 29
Fig. 4.1: The overall implemental flow ………………………31
Fig. 4.2: Circuit characterization flow ………………………32
Fig. 4.3: Three mountain corners ……………………………… 34
Fig. 4.4: An example for explaining rule of similar figure …………………………35
Fig. 4.5: Mountain composition flow of one vector pair …36
Fig. 4.6: Vector applying ……………………………………… 37
Fig. 5.1: Partial normalized peak power trace and peak power metric of GCD……41
Fig. 5.2: Peak power trace and peak power metric trace of 16bit RCA ……………44
Fig. 5.3: Partial power trace and peak power metric trace of AES ………………45


List of Tables
Table 5-1: Results by simulation based scheme……………… 43
Table 5-2: Results by structural scheme……………………… 46
Table 5-3: CPU time………………………………………………… 47

                                

[1] C.-Y. Wang and K. Roy, “Maximum Power Estimation for CMOS Circuits Using Deterministic and Statistical Approaches”, IEEE Transactions on VLSI Systems, pp. 134-140, March 1998
[2] C.-Y. Wang, K. Roy, and T. –l. Chou, “Maximum Power Estimation for Sequential Circuits Using a Test Generation Based Techniques”, Proc. of IEEE Custom Integrated Circuits Conference, pp. 229-232, April 1996
[3] D. Marculescu, R. Marculescu, and M. Pedram, “Information Theoretic Measures for Energy Consumption at the Register-Transfer Level”, Proc. of Int. Symp. Low Power Design, pp. 81-86, April 1995.
[4] S. Gupta and F. N. Najm, “Energy and Peak-Current Per-Cycle Estimation at RTL”, IEEE Transactions on Very Large Scale Integration(VLSI) Systems, v.11 n.4, pp.525-537, Aug. 2003.
[5] S. R. Powell and P. M. Chau, “Estimating Power Dissipation of VLSI Signal Processing Chips: The PFA Technique”, Proc. of VLSI Signal Processing IV, pp. 250-259, Sept. 1990.
[6] H. Mehta, R. M. Owens, and M. J. Irwin, “Energy Characterization Based on Clustering”, Proc. of Design Automation Conf., pp. 702-707, June 1996.
[7] Z. Chen and K. Roy, “A Power Macromodeling Technique Based on Power Sensitivity”, in Proc. Design Automation Conf., pp. 678-683, June 1998.
[8] Q. Wu, Q. Qiu and M. Pedram and C.-S. Ding, “Cycle-Accurate Macro-Models for RT-Level Power Analysis”, IEEE Trans. VLSI Systems, vol. 6, pp. 520-528, Dec. 1998.
[9] H. Kriplani, F. N. Najm, and I. N. Hajj, “Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution”, IEEE Trans. On Computer-Aided Design, pp. 998-1012, Aug. 1995
[10] Y. M. Jiang, A. Krstic, and K. T. Cheng, “Estimation for Maximum Current Through Supply Lines for CMOS Circuits”, IEEE Transactions on Very Large Scale Integration Systems, vol.8, No.1, Feb. 2000
[11] C. T. Hsieh, J. C. Lin, and S. C. Chang, “A vectorless estimation of maximum instantaneous current for sequential circuits”, Proc. of IEEE/ACM Conf. on Computer Aided Design, pp. 537-540, 2004
[12] M.Y. Sum, K.S. Chang, C.C. Weng, and S.Y. Huang, “ToggleFinder: accurate RTL power estimation for large designs”, Proc. of IEEE VLSI Design, Automation and Test, pp.16-19, April 2005.

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