此論文提出一個可以快速切換之適應性迴路頻寬鎖相迴路頻率合成器，其中包含一個整合於晶片中之適應性頻寬迴路濾波器，一個電壓控制震盪器，其中包含一個數位式可調電容陣列，一個可程式除頻器，一個相位頻率偵測器，一個可調式電荷汞，以及數位抖動偵測電路和迴路頻寬決定電路。主要設計目標希望能完成一個快速的頻率切換而且具有高度整合之頻率合成器。在此論文之中，所使用之迴路濾波器採用新的疊加電流鏡之架構，此架構能夠有效的降低電容值的需求，進而降低電容在晶片中佔用之面積。而為了迴路穩定性之考量，電荷汞電流可依照迴路頻寬設定來做調整，以維持迴路整體之穩定性。而抖動偵測電路與迴路頻寬決定電路用來適應性的切換迴路頻寬，進而達成快速鎖定且降低雜訊之操作需求。可程式除頻器則是由多模數除頻器來組成並實現，其中包含了六個除二除三電路，可除數為六十四至一百二十七，而在此鎖相迴路中，除數設定為一百二十。在此高度整合之頻率合成器使用的是台灣積體電路公司零點一八微米金氧半互補式電晶體製程來做實現。量測到的震盪頻率可在十六點九五六億赫茲到十七點七一億赫茲之間。 鎖定時間約為八十四微秒，總共晶片面積為1.188 x 0.998平方厘米，總共量測之電流消耗為二十四點四厘安培。

This thesis proposes the design of a fast-switching frequency synthesizer, which includes an on-chip adaptive-bandwidth loop filter, a VCO with digital varactor array, programmable frequency divider, phase-frequency detector, tunable charge pump, jitter measurement circuit and loop bandwidth decision circuit. The main target is to achieve fast-locking frequency change and highly integration. The on-chip loop filter adopts a cascode current mirror architecture, which effectively shrinks the needs of capacitance, and in advance reduces the occupied area. For the stability of the phase-locked loop, the charge pump current is adjusted according to the loop bandwidth setting. The jitter measurement and loop decision circuit are used for switching the loop bandwidth, and thus achieve a fast-locking behavior. The frequency divider is realized by a multi-modulus prescaler with division number 64 to 127. The fully integrated frequency synthesizer is implemented in TSMC 0.18 μm CMOS process. The measured frequency tuning range is from 1.6956 GHz to 1.710 GHz. The locking time is around 84 μs. The total chip area is 1.188 x 0.998 and the power consumption is 24.4mA.

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