前瞻無線測試平台(HOY)之無線通訊界面設計｜國立清華大學博碩士論文庫

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研究生：	朱銘億 Ming-Yi Chu
論文名稱：	前瞻無線測試平台(HOY)之無線通訊界面設計 Wireless Interface Design for HOY: An Emerging Test Platform
指導教授：	馬席彬 Hsi-Pin Ma
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	79
中文關鍵詞：	后羿測試平台、基頻處理器、取樣頻率漂移、延遲鎖定迴路
外文關鍵詞：	HOY, baseband processor, sampling frequency offset, delay lock loop
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傳統晶片測試的方式採用接觸式探針卡對待測晶片(DUT)進行量測，接觸的測試可能會對晶片本身或是輸入/輸出接點(I/O pads)造成損壞，此外隨著設計複雜度增加，測試成本也隨著提高。為了有效增加晶片測試效能以及降低晶片測試所需成本，許多前瞻的測試方法漸漸被提出。HOY前瞻測試平台提出以無線方式進行測試的構想，其將無線通訊模組嵌入待測晶片中，使測試指令與測試資料可以透過無線通道進行傳送。

本論文提出一個應用於無線通訊介面的基頻處理器，此基頻處理器具有在初始狀態控制RF電路建立自動測試機台(ATE)與待測晶片間的通道連結，以及調整傳送功率大小的功能。根據HOY計畫所自訂的通訊協定，基頻電路可以與MAC層之間順利的做資料傳送與接收。通道編碼與解碼亦能提升通訊品質，使位元錯誤率(Bit Error Rate)在RF傳送距離1公分時小於10-6。此外基頻處理器在接收資料時，同時處理取樣頻率漂移(Sampling Frequency Offset)以及同步的問題。

本論文所提出的基頻處理器已經由FPGA驗證其所具有的功能以及效能，經過邏輯分析儀測量，傳送的位元錯誤率可達到規格所需要的效能，取樣頻率漂移的問題亦可經由基頻電路處理。此外也與HOY通訊模組中的其他數位電路以及類比RF電路整合，此系統亦以FPGA板以及離散元件組成RF電路實現完成，目前已有幾組不同的雛形可提供展示。

HOY計畫已完成將無線通訊模組與HOY測試系統進行整合，整合的待測晶片以記憶體為主要設計的核心電路，無線通訊模組則包含數位電路以及類比RF電路，所完成的待測晶片本身即具有傳送射頻訊號的功能。此整合晶片已於2008年的三月下線，透過國家晶片中心(CIC)使用台積電0.18μm製程製造，晶片大小為17.3mm2，嵌入的HOY通訊模組所佔有的比例為3.64%，而本論文所提出的基頻處理器則是0.75%。

Conventional testing scheme for a chip utilizes probes or sockets between Automatic Test Equipment (ATE) and Device Under Test (DUT), which will cost a lot and damage I/O pads in wafer easily. To improve the quality of chip testing, some advanced testing technologies are discussed, such as wireless testing methodology. A wireless testing concept is proposed in HOY : an emerging test platform. By embedding a wireless communication module into DUT chip, the testing instructions and testing data can be transmitted through wireless channel.

In this thesis, a baseband processor used for wireless communication interface is presented. The proposed baseband processor provides several functions, including controlling RF to build up the wireless channel at initial and controlling transmission power gain during data communication. Channel encoding and decoding also improve the communication robustness. With the coding, BER can be less than 10^-6 for the RF distance of about 1 cm. Moreover, baseband processor deals with some sampling frequency offset problems and synchronization at the initial of receiving data.

The baseband processor has been integrated with some other digital parts and RF module. The whole system is implemented by using FPGA board and discrete component RF module. There are also some prototypes for HOY demonstration.

The latest version in HOY project is the integration of the whole communication module with HOY system. The integration includes digital circuits and analog RF module. The integration has been verified and taped-out in March, 2008. By using memory as DUT core, the overhead of HOY communication module is about 3.64% with the core area 17.3 mm2. The overhead of baseband processor is about 0.75%.

Contents
Introduction                                             1
1 Overview of HOY System . . . . . . . . . . . . . . . . 1
1.1 The Importance of Testing and Challenges . . . . . . 1
1.2 Related Works. . . . . . . . . . . . . . . . . . . . 2
1.3 What Is HOY. . . . . . . . . . . . . . . . . . . . . 3
2 Motivation of the Thesis . . . . . . . . . . . . . . . 3
3 Organization of the Thesis . . . . . . . . . . . . . . 5
HOY System Descriptions and Communications Interface     7
1 HOY System Model . . . . . . . . . . . . . . . . . . . 7
2 The Roadmap for HOY System Prototype . . . . . . . . . 8
3 Baseband Communication Specification I. . . . . . . . 10
4 Baseband Communication Specification II . . . . . . . 11
4.1 Downlink. . . . . . . . . . . . . . . . . . . . . . 13
4.2 Uplink. . . . . . . . . . . . . . . . . . . . . . . 14
5 Baseband Functions  . . . . . . . . . . . . . . . . . 14
System Design for Baseband Processor                    17
1 Design Flow . . . . . . . . . . . . . . . . . . . . . 17
2 Downlink Baseband Architecture. . . . . . . . . . . . 19
3 Uplink Baseband Architecture. . . . . . . . . . . . . 20
4 3-ways Link Handshake Mechanism . . . . . . . . . . . 21
5 Data Synchronization. . . . . . . . . . . . . . . . . 22
Logic Design for Baseband Processor                     25
1 I/O Description . . . . . . . . . . . . . . . . . .. .25
2 Interface with MAC and RF . . . . . . . . . . . . . . 26
2.1 Interface with MAC . . . . . . . . . . . . . . . . .27
2.2 ATE RF Control Signals . . . . . . . . . . . . . . .30
2.3 DUT RF Control Signals . . . . . . . . . . . . . . .35
3 Signal Flow . . . . . . . . . . . . . . . . . . . . . 39
3.1 Initial Setting . . . . . . . . . . . . . . . . . . 39
3.2 Handshake Mechanism . . . . . . . . . . . . . . . . 39
3.3 Data Mode . . . . . . . . . . . . . . . . . . . . . 43
4 Components Design . . . . . . . . . . . . . . . . . . 47
4.1 Forward Error Correction . . . . . . . . . . . . . .47
4.2 Matched Filter . . . . . . . . . . . . . . . . . . .49
4.3 Delay Lock Loop . . . . . . . . . . . . . . . . . . 50
5 Functional Simulation . . . . . . . . . . . . . . . . 57
6 Comparison . . . . . . . . . . . . . . . . . . . . . .58
6.1 Comparison with Adaptive Channel Coding System . . .58
6.2 Comparison with WPAN . . . . . . . . . . . . . . . .60
Implementation, Integration, and Measurement Results    63
1 Hardware Implementation Introduction . . . . . . . . .63
2 Tape-out Chip . . . . . . . . . . . . . . . . . . . . 66
3 Measurement Results . . . . . . . . . . . . . . . . . 68
3.1 The BER Measurement by Using RF Module . . . . . . .68
3.2 The DLL Function Verification . . . . . . . . . . . 70
4 RF Integration Prototype . . . . . . . . . . . . . . .71
Conclusions and Future Works                            73
1 Conclusion . . . . . . . . . . . . . . . . . . . . . .73
2 Future Work . . . . . . . . . . . . . . . . . . . . . 74

                                

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