在這篇論文中，我們提出了一個在乘積式可程式化邏輯閘架構上的映成演算法。我們的演算法主要分成了兩個步驟：第一步驟，映成至單一輸出的乘積式可程式邏輯陣列(single-output PLA)，第二步驟，將先前第一步驟之單一輸出的乘積式可程式邏輯陣列合併成為多重輸出的乘積式可程式邏輯陣列(multi-output PLA)。而在映成階段時，基於先前之研究成果[4]，我們提出了Look-Up-Table based 映成演算法。我們使用了先前存在之LUT映成演算法中對於最小化面積和最小化延遲的優點來完成我們的映成演算法。同時我們也對於給定 (i, p, o)-PLA 架構時，在於映成階段如何去選擇單一輸出的乘積式可程式邏輯陣列輸入和乘積的限制條件的問題加以探討並提出方法。在實驗結果上相對於先前所發表的方法(TEMPLA)，在面積與延遲上均有所改善。

In this thesis, we propose a technology mapping algorithm
for CPLD architectures. Our algorithm proceeds in two phases:

mapping for single-output PLAs and packing for multiple-output PLAs.

In the mapping phase, based on the results in [4],

we propose a Look-Up-Table (LUT) based mapping algorithm.

We will take advantage of existing LUT mapping

algorithms for area and depth minimization.

We also study, for a given (i, p, o)-PLA

block structure, the problem of selecting the values of input and product

term constraints for mapping for single-output PLA.

Benchmark results show that our algorithm produce

better results in terms of area and depth as compared to those by TEMPLA.

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Design Automation Conference, pp. 698-703, June 1998.
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ACM/SIGDA International Symposium on Field Programmable
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IEEE Design and Test of Computers, Vol. 9, pp. 34-39, Dec. 1992.
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IEEE Custom Integrated Circuits Conference,
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ACM Workshop on Field Programmable Gate Array, pp. 9-14 1992.
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“Empirical Study of the Effect of Cell Granularity on FPGA Density and
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IEEE Transaction on Computer-Aided Design of Integrated Circuit and Systems, Vol. 13, No. 1, pp. 1-11, January 1994.
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28th ACM/IEEE Design Automation Conference, pp. 227-233, June 1991.
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ACM Transaction on TODAES, Vol. 1, No. 2, pp. 145-162, April 1996.
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“SIS: A System for Sequential Circuit Synthesis”,
Technical Report UCM/REL M92/41, Electronics Research Lab., Department of Electrical Engineering and Computer Science, University of California, Berkeley, 1992.
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“DAG-Map: Graph-Based FPGA technology Mapping for Delay Optimization”,
IEEE Design and Test of Computers, Vol. 9, pp. 7-20, 1992.
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“Architecture of Field-Programmable Gate Arrays: the effect of logic block functionality on area efficiency”,
IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, pp. 1217-1225, Oct. 1990.
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“Architecture of Field-Programmable Gate Arrays”,
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