考慮源汲極寄生電阻效應，蕭特基金氧半電晶體成為下世代奈米級金氧半電晶體發展的必然趨勢。但是其元件的發展仍存在許多挑戰，進而限制了它在互補式金氧半電路上更進一步的應用。本論文主要探討蕭特基金氧半電晶體的基本元件特性，利用二維元件模擬軟體分析其相關的元件設計參數，進行元件設計最佳化。進而提出創新的結構來改善其繼續微縮的可行性，並探討蕭特基金氧半元件在雜訊方面的限制及可能機制。
在蕭特基金氧半電晶體的元件設計中，雙向導通行為是最重要的參考因素，進一步探討各項元件參數對電性行為的影響，可以發現金屬源汲極的蕭特基能障高度、源汲極與閘極的偏移量、閘氧層厚度皆對元件的電流特性有顯著的影響。若適當地選取這些元件參數，可以對蕭特基金氧半電晶體元件進行最佳化的設計。對於具備摻雜析離的蕭特基金氧半元件，也詳盡的探討析離層對元件特性的影響。這層高濃度的摻雜析離層雖可改善元件的特性，但在短通道微縮時，會因高濃度的通道摻雜及超薄閘氧層的應用，使得元件的雙向導通行為顯著退化。
為了因應蕭特基金氧半元件繼續微縮的可行性，提出一種具雙重功函數閘極的創新蕭特基元件架構，並能結合既有互補式金氧半製程步驟來製作。此雙重功函數閘極結構能有效改善於薄閘氧層時的雙向導通退化行為，在蕭特基元件的閘氧層及通道長度繼續微縮時，仍能同時改善短通道效應及雙向導通行為。同時，此雙重功函數閘極的架構可結合摻雜析離層技術將蕭特基電晶體進一步最佳化。
而在蕭特基金氧半元件的雜訊行為上，依其製程觀點及特殊電性行為，提出潛在的雜訊來源機制。蕭特基金氧半電晶體除了擁有與傳統金氧半元件相同的雜訊來源外，會因金屬源汲極的引入，增加從接面缺陷所造成的雜訊，使得蕭特基元件的雜訊將大於傳統金氧半電晶體。特別的，這些雜訊會因在不同電壓操作、不同的源汲極金屬矽化物，而有不同的行為。

As MOSFETs scale into nanoscale regime, extensively minimizing source/drain depth limits the improvement of driving drain current due to the increased series resistance. By eliminating implanted ultra-shallow junctions, the metallic Schottky Barrier MOSFET (SBMOS) becomes a most attracting candidate in deep sub-50 nm regime. The objective of this dissertation is to explore in depth the design and application of SBMOS devices using two-dimensional numerical simulations for the use of SBMOS in future CMOS technologies.
The current-voltage characteristics of SBMOS are highly dependent on Schottky barrier height, source/drain to gate misalignment, and gate-oxide thickness. Ambipolar conduction of SBMOS can be optimized by an appropriate choice of these primary parameters. A dopant segregated layer can efficiently modify the Schottky barriers to suppress the off-state ambipolar conduction and simultaneously to enhance the on-state driving current. However, apparent degradations of ambipolar conduction in SBMOS are observed when a thin gate-insulator or a heavy halo profile is used for scaled short-channel devices. A novel Dual Workfunction Gate architecture is innovated to optimize SBMOS by tailoring Schottky barrier distributions through vertical gate engineering. An optimal SBMOS can be achieved with enhanced driving current, minimized ambipolar conduction and suitable short-channel effect.
This study also elucidates the latent noise mechanisms in SBMOS devices. The complex noise problems in SBMOS arise from the particular ambipolar conduction and the additional interface states at metallic source/drain junctions. In addition to the excess noise of conventional MOSFETs, the interface traps at the metallic source/drain are keys to the overall noise characteristics of SBMOS. Most possible noise sources under various operating conditions are summarized herein to provide a comprehensive understanding of how noise potentially limits the practical applications of SBMOS devices.

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