全數位式鎖相迴路相較於傳統式與數位式鎖相迴路，有著更好的雜訊容忍度，隨著先進製程的演進，電路晶片設計可更容易跟隨著製程一起縮小面積。
本論文提出一震盪頻率為4.825GHz具三角積分調變除法器之量化雜訊消除之基於時間數位轉換器浮點數型全數位式鎖相迴路，其中時間數位轉換器電路設計採用基於連續漸進式類比數位轉換器之全新架構設計，其高時間解析度可大幅提升輸出頻譜之相位雜訊表現。
數位濾波器之電路設計採用左移/右移(Left/Right Shifter)電路取代乘法器以大幅降低晶片面積並透過Scan Chain電路設計以大幅提升迴路鎖定時間。
於數位控制震盪器採用二階三角積分調變器以大幅降低數位類比轉換器之量化雜訊對輸出頻譜的影響，於壓控震盪器則採用切換式電容以調變電容電感式壓控震盪器之震盪頻率範圍。最後透過十六位元三階三角積分調變器以調變除法器達成所需之除數解析度，透過以上子電路建構出完整的全數位式鎖相迴路電路架構。
論文開頭以簡介各種鎖相迴路基本架構並進行比較，接著依序講解全數位式鎖相迴路之數學模型、設計流程並進行各子電路雜訊分析以分析晶片規格，最後採用台積電65奈米製程技術進行實體電路架構分析、模擬佈局與晶片下線考量，並以本篇論文設計進行統合性的結論，整體系統晶片功耗為17.40768mW、晶片總面積為1.07 mm X 0.78 mm。

All-Digital Phase-Locked Loop have better noise tolerance than Conventional & Digital Phase-Locked Loop. With the evolution of advanced process, circuit design can scale down with the process more easily.
We propose a 4.825GHz Fractional-N TDC-Based All-Digital Phase-Locked Loop w/i Sigma-Delta Modulator Noise Cancellation in this thesis. The circuit design of Time to Digital Converter is based on a Successive Approximation Analog to Digital Converter (SAR ADC). The brand new architecture design of TDC can significantly increase the phase noise performance of output spectrum by its high time resolution.
The circuit design of Digital Loop Filter is implemented by Left/Right Shifter circuit instead of Multiplier circuit to significantly reduce the chip area and greatly accelerate the locking time of system through the Scan Chain circuit design.
The Digital Control Oscillator is implemented by a second-order sigma-delta modulator to reduce the effect of DAC quantization noise on the output spectrum. As the Voltage Control Oscillator, switched capacitor tuning banks are used to modulate the tuning range of LC tank VCO. The desired divisor resolution of divider is modulated by sixteen-bit third-order sigma-delta modulator in the end. The above sub-circuits construct a complete All-Digital Phase-Locked Loop circuit architecture.
This thesis begins from a brief introduction and comparison to various kinds of basic Phase-Locked Loop architecture. Then explains the mathematical model and design flow of All-Digital Phase-Locked Loop sequentially. Besides, the noise analysis of each sub-circuits is performed to analyze the system specifications.
Finally, the physical circuit architecture analysis, layout considerations and Pre/Post simulations is implemented by the TSMC 65nm process. Then concludes the complete circuit design in this thesis. The overall system power consumption is 17.40768mW, and the total system area is 1.07 mm X 0.78 mm.

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