軟硬體協同設計之高效能多核心向量圖形加速系統

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研究生：	陳碩鴻 Chen, Shuo-Hung
論文名稱：	軟硬體協同設計之高效能多核心向量圖形加速系統 HW/SW Co-Design of High-Performance Multi-Core Vector Graphics System
指導教授：	鍾葉青 Chung, Yeh-Ching
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	31
中文關鍵詞：	軟硬體協同設計、向量圖形、嵌入式系統
外文關鍵詞：	HW/SW Co-Design, Vector Graphics, Embedded System
相關次數：	點閱：3 下載：0
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本作品藉由整合具有高速運算能力的硬體加速器，以軟硬體協同設計的方法，為向量圖形設計一組與軟體函式庫搭配的硬體系統。使目標程式有較純軟體實作快十倍以上的效能增益。除此之外，本作品也包含一套軟硬體整合平台，此平台可以幫助系統開發者建立可靠的軟硬體整合系統，並可在此平台上進行系統的功能驗證與效能分析。

This work presents a hardware-software co-design methodology to design a hardware accelerator that integrated with software library to speed-up existing vector graphics applications, and the resulting system is ten times faster than optimized software implementation. In order to verify the integrated system, a new hardware-software integration platform is purposed to help designer developing hardware-software cooperated architectures and performing quick performance evaluations and functional verifications.

Chapter 1 Introduction ........................................................................................................................ 1
Chapter 2 Background ........................................................................................................................ 3
    2.1 Vector Graphics ................................................................................................................ 3
    2.2 OpenVG Standard …………………………………………..…………………......…… 4
    2.3 OpenVG Rendering Pipeline ……………………………....…….…………….......…… 4
Chapter 3 Design Methodology ……………………………………….....…………………............ 6
    3. 1 Hardware-Software Co-Design ………………………………….....…………......…… 6
        3.1.1 Hardware-Software Partition …………………………………..…….……...... 6
            3.1.1.1 Profiling ................................................................................................6
            3.1.1.2 Analysis ................................................................................................6
            3.1.1.3 Hardware-Software Interface ...............................................................7
        3.1.2 Software Design ……………………………………………………..……… 7
            3.1.2.1 Software Components……………..............................................…… 7
            3.1.2.2 Library Porting….................................................................…........… 8
        3.1.3 Hardware Design …………………………………………………………... 8
            3.1.3.1 Reference Model …………………………………………..........…... 8
            3.1.3.2 Accelerator Design …………………………………………….......... 8
            3.1.3.3 Verification……………………………………....................……... 8
        3.1.4 Hardware-Software Integration ……………………………………………. 9
            3.1.4.1 Hardware-Software Co-Simulation ………………………………… 9
            3.1.4.2 Hardware-Software Co-Emulation …………………………………. 9
            3.1.4.3 System Prototype …………………………………………………… 9
        3.1.5 Hardware-Software Co-Verification ……………………………………..... 9
            3.1.5.1 Simulated Platform ………………………………………………. 10
            3.1.5.2 EASY-CAP9 - Hardware-Software Co-Simulation Platform …...... 11
            3.1.5.3 FPGA-CAP9 - Hardware-Software Co-Emulation Platform ……... 12
Chapter 4 Implementation ………………………............................................................... 14
    4.1 Hardware-Software Partition …………………………………………………….. 14
        4.1.1 Path-to-Stroke Conversion ……………………………………………... 15
        4.1.2 Coordinates Transformation …………………………………………….... 15
    4.2 Software Implementation ………………………………………………………... 16
        4.2.1 Vector Graphics Applications ……………………………………………. 16
        4.2.2 OpenVG Library ……………………………………………………….. 17
        4.2.3 Linux Device Driver …………………………………………………….... 18
    4.3 Hardware Implementation ……………………………………………………... 18
        4.3.1 Accelerator Design ……………………………………………………... 18
            4.3.1.1 Bus Accessing Control Unit ………………………………………18
            4.3.1.2 Storage Unit ……………………………………………………….. 20
            4.3.1.3 Central Control Unit …………………………………………...... 21
            4.3.1.4 Segment Processing Unit ………………………………………... 21
            4.3.1.5 Coordinate Transformation Unit ………………………………... 23
        4.3.2 Multi-Core Architecture ………………………………………………... 23
        4.3.3 Hardware Verification ………………………………………………….. 23
    4.4 Hardware-Software Integration ………………………………………………... 24
    4.5 Hardware-Software Co-Verification …………………………………………... 26
        4.5.1 OpenVG Accelerator in EASY-CAP9 ………………………………..... 26
        4.5. 2 OpenVG Accelerator in FPGA-CAP9 ……………………………….... 26
Chapter 5 Experimental Results ………………………………………………………… 27
Chapter 6 Conclusion …………………………………………………………………… 29
Reference ………………………………………………………………………………... 30

                                

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