在本篇論文中，我們提出了一個方法來產生匯流排通訊架構(bus communication architecture)，使其在滿足給定的系統效能限制下具有較低的耗能。
我們的方法主要分為兩個步驟。首先我們會透過平面規劃(floorplanning)來協助產生一個初步的答案。對於每一個候選的平面規劃結果(floorplan)，我們先挑選一個匯流排架構，並對其估計系統效能及消耗的能量。在此步驟中所產生具有最小耗能並滿足系統效能限制的匯流排架構即為初步的答案。第二個步驟是利用模擬退火法(Simulated Annealing)並根據前一步驟所得到的初步結果來進一步尋找更好的答案。
實驗結果顯示出利用我們的方法，只需要5% 的效能下降即可減少約60% 的能量消耗，這指出了我們的方法是很有效的。另一方面，我們用來的測試的例子最多含有15個矽智財(Intellectual Properties)，均可在數分鐘之內跑完，這也顯示了我們方法的效率。

In this thesis, we present a methodology to generate floorplan-aware bus-based communication architectures. The methodology aims to minimize communication energy while the user-specified performance constraints can be satisfied.
Our methodology can be roughly divided into two steps. The first step is to generate an initial solution through a floorplanning process. In this step, for each candidate floorplan, we will choose a bus architecture first, and then estimate its communication energy and performance. Among the bus architectures which are accepted in this step and satisfy user-specified performance constraints, the one with smallest communication energy will be selected as the initial solution. In the second step, our methodology will further try to search for better solutions (with even smaller communication energy) based on the initial solution through a simulated annealing based refinement process.
We have implemented our methodology and the experimental results show that only 5% performance degradation is required to make at least 59.78% reduction of communication energy. This indicates that our methodology is very effective. On the other hand, our methodology is also efficient because the bus architecture of each test case (containing up to 15 IP cores) can be generated in a few minutes.

REFERENCES

[1] M. Drinic, D. Kirovski, S. Meguerdichian and M. Potkonjak, “Latency-guided on-chip bus network design,” in Proc. Int. Conf. on Computer-Aided Design, pp. 420-423, 2000.
[2] S. Pasricha, N. Dutt, E. Bozorgzadeh, and M. Ben-Romdhane, “Floorplan-aware automated synthesis of bus-based communication architectures,” in Proc. Design Automation Conference, pp. 565-570, 2005.
[3] K. Lahiri, A. Raghunathan, G. Lakshminarayana and S. Dey, “Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips,” in Proc. Design Automation Conference, pp. 513-518, 2000.
[4] C. Shin, Y.-T. Kim, E.-Y. Chung, K.-M. Choi, J.-T. Kong and S.-K. Eo, “Fast exploration of parameterized bus architecture for communication-centric SoC design,” in Proc. Design Automation and Test in Europe, pp. 352–357, 2004.
[5] R. Lu and C.-K. Koh, “A high performance bus communication architecture through bus splitting,” in Proc. Asia and South Pacific Design Automation Conf., pp. 751–755, 2004.
[6] W.-B. Jone, J.-S. Wang, H.-I. Lu, I.-P. Hsu and J.-Y. Chen, “Design theory and implementation for low-power segmented bus systems,” in ACM Transactions on Design Automation of Electronic Systems, 8(1), pp. 38–54, Jan., 2003.
[7] R. E. Gomory and T. C. Hu, “Multi-terminal network flows,” Journal of the Society of Industrial and Applied Mathematics, 9(4), pp. 551-570, Dec. 1961.
[8] C.-T. Hsieh and M. Pedram, “Architectural power optimization by bus splitting,” in Proc. Design Automation and Test in Europe, pp. 612–616, 2000.

[9] J. Hu, Y. Deng and R. Marculescu, “System-level point-to-point communication synthesis using floorplanning information,” in Proc. Int. Conf. on VLSI Design, 573-579, 2002.
[10] K. Lahiri, A. Raghunathan and S. Dey, “Performance analysis of systems with multi-channel communication architectures,” in Proc. Int. Conf. on VLSI Design, pp. 530–537, Jan. 2000.
[11] S. Kirkpatrick, C. D. Gelatt and M. P. Vecchi Jr., “Optimization by simulated annealing,” Science, 200(4589), pp. 671-680, 1983.
[12] T.-C. Chen and Y.-W. Chang, “Modern floorplanning based on fast simulated annealing,” in Proc. ACM Int. Symp. on Physical Design, pp.104-112, 2005.
[13] J. B. Kruskal, ” On the shortest spanning subtree of a graph and the travelling salesman problem,” in Proc. American Math. Society 7, pp.48-50, 1956.