對於未來金氧半電容器有潛力的是氧化鏑(Dy2O3)，在本實驗中，以氧化鏑(Dy2O3)作為閘極的電容器和場效電晶體，成功地被製作，其中最大的電子遷移率為329 cm2/V-s。氧化鏑(Dy2O3) 的依時性介電崩潰(TDDB) 對於溫度和電壓的影響也作了分析，韋布斜率(b)的值與電容的面積大小沒有相關，而當電容厚度增加時，韋布斜率(b)也隨著變大。氧化鏑(Dy2O3) 的依時性介電崩潰(TDDB) 的機制可以利用E model來說明，在E model中所求得的活化能Ea，與電場為性線的關係，而場加速因子γ與溫度是獨立的。

　　Dy2O3 is a promising candidate for future MOS gate dielectric applications. In this work, MOS capacitors and MOSFETs with Dy2O3 gate dielectric were fabricated. The maximum electron mobility is 329 cm2/V-s. The time dependent dielectric breakdown (TDDB) of Dy2O3 as a function of electric field and temperature was studied. It was observed that the Weibull slopes were independent of capacitor area. The Weibull slope increases with increasing Dy2O3 thickness. The TDDB of Dy2O3 follows the E model. The activation energy Ea is linearly dependent on the electric field and the field acceleration parameter γ is independent of temperature.

Reference

[1] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Makamura, M. Saito, and H. Iwai, “1.5 nm direct-tunneling gate oxide Si MOSFET’s,” IEEE Trans. Electron Devices, vol. 43, pp. 1233, 1996.
[2] G. D. Wilk, and R. M. Wallace, “Electrical properties of hafnium silicate gate dielectrics deposited directly on silicon,” Appl. Phys. Lett., vol. 74, no. 19, pp. 2854, 1999.
[3] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “Hafnium and zirconium silicates for advance gate dielectrics,” J. Appl. Phys., vol. 87, no. 1, pp. 484, 2000.
[4] B. H. Lee, L. Kang, R. Nieh, W. J. Qi, and J. C. Lee, “Thermal stability and electrical characteristics of ultrathin hafnium oxide gate dielectric reoxidized with rapid thermal annealing,” Appl. Phys. Lett., vol. 76, no. 14, pp. 1926, 2000.
[5] S. Lee “High Quality Ultra Thin CVD HfO2 Gate Stack with Poly-Si Gate Electrode,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 31, 2000.
[6] L. Kang, Y. Jeon, K. Onishi, B. H. Lee, W. J. Qi, R. Nieh, S. Gopalan, and J. C. Lee, “Single-layer Thin HfO2 Gate Dielectric with n+-Polysilicon Gate,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 44, 2000.
[7] Kang L., Onishi K., Jeon Y., Byoung Hun Lee, Kang C., Wen-Jie Qi, Nieh R., Gopalan S., Choi R., and Lee J.C. “MOSFET Device with Polysilicon on Single-Layer HfO2 high-K Dielectrics,” IEDM Tech. Dig., pp. 35, 2000.
[8] Lee C.H., Luan H.F., Bai W.P., Lee S.J., Jeon T.S., Senzaki Y., Roberts D., and Kwong D.L.“MOS Characteristics of Ultra Thin Rapid Thermal CVD ZrO2 and Zr Silicate Gate Dielectrics”, IEDM Tech. Dig., pp.27, 2000.
[9] H. Lee, S. Jeon, and H. Hwang, “Electrical characteristics of a Dy-doped HfO2 gate dielectric,” Appl. Phys. Lett., vol. 79, no. 16, pp. 2615, 2001.
[10] D. A. Neumayer, and E. Cariter, “Materials characterization of ZrO2-SiO2 and HfO2-SiO2 binary oxides deposited by chemical solution deposition,” J. Appl. Phys., vol. 90, no. 4, pp. 1801, 2001.
[11] A. Callegari, E. Cariter, H. F. Okorn-Schmidt, and T. Zabel, “Physical and electrical characterization of Hafnium oxide and Hafnium silicate sputtered films,” J. Appl. Phys., vol. 90, no. 12, pp. 6466, 2001.
[12] S. J. Lee ,and Terano T. Moriya, “Performance and Reliability of Ultra Thin CVD HfO2 Gate Dielectrics with Dual Poly-Si Gate Electrodes,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 133, 2001.
[13] R. Choi., and Givens M “High-Quality Ultra-thin HfO2 Gate Dielectric MOSFETs with TaN Electrode and Nitridation Surface Preparation,” IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 15, 2001.
[14] Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, and J. Lim, “Conventional n-channel MOSFET device using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode,” IEDM Tech. Dig., pp. 455, 2001.
[15] W. Zhu ,Endoh T., and Kinoshita K. “HfO2 and HfAlO for CMOS: Thermal Stability and Current Transport,” IEDM Tech. Dig., pp. 463, 2001.
[16] C. Hobbs , Y. H. Song, J. I. Han, J. W. Kim, J.H. Park, and Kim “80nm Poly-Si Gate CMOS with HfO2 Gate Dielectric,” IEDM Tech. Dig., pp. 651, 2001.
[17] M. Gutowski, J. E. Jaffe, C. L. Liu, M. Stoker, R. I. Hegde, R. S. Rai, and P. J. Tobin, “Thermodynamic stability of high-K dielectric metal oxide ZrO2 and HfO2 in contact with Si and SiO2,” Appl. Phys. Lett., vol. 80, no. 11, pp. 1897, 2002.
[18] B. K. Park, J. Park, M. Cho, C. S. Hwang, K. Oh, Y. Han, and D. Y. Yang, “Interfacial reaction between chemically vapor-deposited HfO2 thin films and a HF-cleaned Si substrate during film growth and postannealing,” Appl. Phys. Lett., vol. 80, no. 13, pp. 2368, 2002.
[19] L. Kang, B. H. Lee, W. J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, and J. C. Lee, “Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric,” IEEE Electron Device Lett., vol. 21, no. 4, pp. 181, 2000.
[20]T. Gougousi, M. J. Kelly ,and G. N. Persons,“The role of the OH species in high-k/polycrystalline silicon gate electrode interface reactions,”Appl. Phys. Lett., vol.80, pp. 4419,2002.
[21]J. A. Gupta, D. Landheer, J. P. McCaffrey ,and G. I. Sproule, “Gadolinium silicate gate dielectric films with sub-1.5 nm equivalent oxide thickness ,”Appl. Phys. Lett., vol. 78, pp. 1718, 2001.
[22]R. L. Nigro,V. Raineri,and C. Bongiorno,“Dielctric properties of Pr2O3 high-k films grown by metalorganic chemical vapor deposition on silicon, ”Appl. Phys. Lett., vol. 83, pp. 129, 2003.
[23] S. I. Ohmi, H. Yamamoto, J. Taguchi, K. Tsutsui ,and H. Iwai,“ Effects of Post Dielectric Deposition and Post Metallization Annealing Processes on Metal/Dy2O3/Si(100) Diode Characteristics,”J. JAP, vol. 43, pp. 1873, 2004.
[24] H. Iwai, S. Ohmi, S. Akama, C. Ohshima, A. Kikuchi, I. Kashiwagi, J. Taguchi, H. Yamamoto, J. Tonotani, Y. Kim, I. Ueda, A. Kuriyama, and Y. Yoshihara,“Advanced Gate Dielectric Materials for Sub-100nm CMOS,”IEDM Tech. Dig., pp. 625, 2002.
[25]S. Jeon, K. Im, H. Lee, H. Sim, S. Choi, T. Jang, and H. Hwang, “Excellent Electrical Characteristics of Lanthanide(Pr, Nd, Sm, Gd, and Dy)Oxide and Lanthanide-doped Oxide for MOS gate Dielectric Applications,” IEDM Tech. Dig., pp. 471, 2001.
[26]S. Jeon, and H. Hwang,“Effect of hygroscopic nature on the electrical characteristics of lanthanide oxides(Pr2O3, Sm2O3, Gd2O3, and Dy2O3),”J. Appl. Phys., vol. 93, pp. 6393, 2003.
[27]J. Robertson, and J. Vac. Sci., Tchnol.B18, pp. 1785, 2000.
[28]S. Jeon, K. Im, H. Yang, H. Sim, H. Lee, S. Choi, T. Jang, and H. Hwang, “Excellent Electrical Characteristics of Lanthanide(Pr, Nd, Sm, Gd, and Dy)Oxide and Lanthanide-doped Oxide for MOS gate Dielectric Applications, IEDM Tech.Dig., pp.475, 2000.
[29] J. L. Autran, R. Devine, C. Chaneliere, and B. Balland, “Fabrication and characterization of Si-MOSFET’s with PECVD amorphous Ta2O5 gate insulator,” IEEE Electron Device Lett., vol. 18, pp. 447, 1997.
[30] C. Chaneliere, S. Four, J. L. Autran, R. A. B. Devine, and N. P. Sandler, “Properties of amorphous and crystalline Ta2O5 thin films deposited on Si from Ta(OC2H5)5 precursor,” J. Appl. Phys., vol. 83, no. 9, pp. 4823, 1998.
[31] Q. Lu, D. Park, A. Kalnitsky, C. Chang, C. C. Cheng, S. P. Tay, T. J. King, and C. Hu, “Leakage Current Comparison Between Ultra-Thin Ta2O5 Films and Conventional Gate Dielectrics,” IEEE Electron Device Lett., vol. 19, no. 9, pp. 341, 1998.
[32] D. Park, Y. King, Q. Lu, T. J. King, C. Hu, A. Kalnitsky, S. P. Tay, and C. C. Cheng, “Transistor Characterization with Ta2O5 Gate Dielectric,” IEEE Electron Device Lett., vol. 19, no. 11, pp. 441, 1998.
[33]B. C. Lai, N. Kung, and J. Y. Lee, “A study on the capacitance-voltage characteristics of metal-Ta2O5-silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications,” J. Appl. Phys., vol. 85, no. 8, pp. 4087, 1999.
[34] J. C. Yu, B. C. Lai, and J. Y. Lee, “Fabrication and Characterization of Metal-Oxide-Semiconductor Field-Effect Transistors and Gated Diodes Using Ta2O5 Gate Oxide,” IEEE Electron Device Lett., vol. 21, no. 11, pp. 537, 2000.
[35] B. C. Lai, J. C. Yu, and J. Y. Lee, “Ta2O5/Silicon Barrier Height Measured from MOSFETs Fabrication with Ta2O5 Gated Dielectric,” IEEE Electron Device Lett., vol. 22, no. 5, pp. 221, 2001.
[36] D. K. Schroder, “Semiconductor material and devic characteristics,” Wiley, Arizona, 1998.
[37] S. M. Sze, “Physics of Semiconductor Device, 2nd ed., ” Wiley, New York, 1981.
[38] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., vol. 40, no. 1, pp. 278, 1969.
[39] K. C. Kao, and W. Hwang, Electrical Transport in Solids, Pergamon, New York, 1981.
[40] P. Mark, and W. Helfrich, “Space-Charge-Limited Currents in Organic Crystals,” J. Appl. Phys. vol. 33, pp.205 1965.
[41] M.A. Lampert and P. Mark, Current Injection in Solids, Academic, New York, 1970.
[42] M.A. Lampert, “Simplified Theory of Space-Charge-Limited Currents in an Insulator with Traps,” Phys. Rev., vol. 103, pp.1648, 1956.
[43] Y. Kim, S. Ohmi, K. Tsutsui and H. Iwai “Space-Charge-Limited Currrent Conduction in La2O3 Thin Tilms Deposited by E-BEAM Evaporation after Low Temperature Dry-Nitrogen Annealing,” Phys. Rev., vol. 106, pp.1548.
[44] M. Depas, T. Nigam, and M. M. Heyns, “Soft breakdown of ultra thin gate oxide layers,”IEEE Trans. Electron Devices vol. 43, pp. 1499, 1996.
[45] E. Rosenbaum, J. C. King, and C-M Hu, “Accelerated testing of SiO2 reliability,” IEEE Trans. Electron Devices vol. 43, pp. 70, 1996.
[46] Young Hee Kim, Onishi K., Chang Seok Kang, Hag-Ju Cho, Rino Choi, Krishnan S., Akbar M.S.,and Lee J.C.,” Thickness dependence of Weibull slopes of HfO2 gate dielectrics,” IEEE Electron Device Lett., vol.24 ,pp.40 ,2003.
[47] Y. H. Kim, K. Onishi, C. S. k. Kang, H. J. Cho, R. Nieh, S., C. R. Gopalan, J. Han, S. Krishnan ,and J.C. Lee;” Area dependence of TDDB characteristics for HfO2 gate dielectrics,”
IEEE Electron Device Lett., vol. 23, pp. 594, 2002.
[48] T. Nigam, R. Degraeve, G. Groeseneken, M.M. Heyns, and H.E. Maes, “Constant current charge-to-breakdown: Still a valid tool to study the reliability of MOS structures?,” in Proc. IRPS, pp. 62, 1998.
[49] R. Degraeve, G. Groeseneken, R. Bellens, J. L. Ogier, M. Depas, P. J. Roussel, and H. E. Maes, “New insights in the relation between electron trap generation and the statistical properties of oxide breakdown,” IEEE Trans. Electron Devices, vol. 45, pp. 904, 1998.
[50] D. Crook, “Method of determining reliability screens for time dependent dielectric breakdown,”in Proc. IEEE-IRPS, vol. 17, pp. 1, 1979.
[51] E. S. Anolick ,and G. Nelson, “Low field time dependent dielectric integrity,” in Proc. IEEE-IRPS, vol.7, pp. 8, 1979.
[52] A. Berman, “Time zero dielectric reliability test by a ramp method,” in Proc. IEEE-IRPS, vol. 19, pp. 204, 1981.
[53] J. W. Mcpherson and D. A. Baglee, “Acceleration parameters for thin gate oxide stressing,” in Proc. IEEE-IRPS, vol. 23, pp. 1, 1985.
[54] M. A.Yassine, H. E. Nariman, M. McBride, M. Uzer,and K. R. Olasupo,“Time dependent breakdown of Ultrthin gate oxide,” IEEE Trans. Electron Devices, vol. 47, pp. 1416, 2000.
[55] J. McPherson, V. Reddy, K. Banerjee, and H. Le, “Comparison of E and 1/E TDDB Models for SiO2 under long-term/low field test conditions,” IEDM Tech. Dig., pp. 17, 1998.
[56] I. C. Chen, S. Holland, and C. Hu, “A quantitative model for time-dependent breakdown in SiO2,”in Proc. IEEE-IRPS, vol. 23, pp. 24, 1985.
[57] J. Lee, I. C, Chen, and C. Hu, “Statistical modeling of silicon dioxide reliability,”in Proc. IEEE-IRPS, vol. 26, pp. 131, 1988.
[58] C. C.Chen, C. Y.Chang,C. H. Chien, and T. Y. Huang, “Temperature –accelerated dielectric breakdown in ultrathin gate oxides,” Appl. Phys. Lett.,vol. 74, pp. 3708, 1999.
[59] K. Eriguch and M. Niwa, “Temperature and stress polarity-dependent dielectric breakdown in ultrathin gate oxides,” Appl. Phys. Lett., vol. 73, pp. 1985, 1998.
[60] J. S. Suehle, P. Chaparala, C. Bessick, W. M. Miller, and K. C. Boyko, “Field and Temeprature Acceleration of Time-Dependent Dielectric Breakdown in Intrinsic Thin SiO2,”in Proc. IEEE-IRPS, vol. 32, pp. 120, 1994.
[61]M. Kimura, ”Field and temeperature acceleration model for time-dependent dielectric breakdown, ” IEEE Trans. Electron Devices, vol. 46, pp. 220, 1999.
[62] Y. Taur and T. H. Ning , Fundamentals of Modern VLSI Devices, 1st ed. (Cambridge, 1998)
[63] S. Takagi, A. Toriumi, M. Iwase, and H. Tango, “On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration”, IEEE Transaction on Electron Devices, vol. 41, pp. 2357, 1994.
[64] C. G. Sodini, T. W. Ekstedt, and J. L. Moll, “Charge accumulation and mobility in thin dielctric MOS transistors,” Solid State Electron., vol. 25, pp. 833, 1982.
[65]W. K. Henson, K. Z. Ahmed, E. M. Vogel, J. R. Hauser, J. J. Wortman, R. D. Venables, M. Xu, and D. Venables, ”Estimating oxide thickness of tunnel oxide down to 1.4 nm using conventional capacitance-voltage measurement on MOSD capacitors”, IEEE Electron Device Lett., vol. 20, pp. 179, 1999.
[66] W. J. Zhu, J. P. Han, and T. P. Ma, “Mobility measurement and degradation mechanisms of MOSFETs made with ultra-thin high-k □ dielectrics”, IEEE Transaction on Electron Devices, vol. 51, pp. 98, 2004.