液晶顯示器佔用的空間小、輻射量低、不產生高熱等優點，使得液晶顯示器慢慢取代了傳統的陰極射線管顯示器，成為消費者的新選擇。然而，由於液晶顯示器和陰極射線管顯示器的顯像原理有所不同，液晶顯示器需要多一個介面來將電腦輸出的類比訊號轉成數位訊號。其中，由水平同步時脈產生的圖素速率時脈的品質，將會嚴重影響畫面的品質。本研究論文將著重在如何藉由此頻率較低之水平同步時脈，來產生出一多相位高頻率高品質的圖素速率時脈。

要達到時脈倍頻之效果，鎖相迴路為目前最常用的電路，但傳統的鎖相迴路電路會受到迴路頻寬的限制，使得其時脈抖動無法有效抑止。從系統觀點而言，為使系統達到穩定，鎖相迴路之迴路頻寬要遠小於輸入時脈之頻率；對於輸入時脈之抖動，將迴路頻寬設得越小，越能有效降低輸入時脈抖動對輸出時脈的影響；然而，對於壓控振盪器產生之抖動，將迴路頻寬設得越大，則越能有效抑止壓控振溫器產生之抖動對輸出時脈的影響。因此，要同時抑止輸入時脈和壓控振盪器對輸出時脈之抖動，對迴路頻寬的選擇是相矛盾的。

為了解決迴路頻寬所造成的限制，我們提出了以一個類比鎖相迴路及一個直接數位頻率合成器(Direct Digital Frequency Synthesizer ; DDFS)結合而成的架構來產生多重相位低抖動之圖素速率時脈，並且能快速地和水平同步訊號同步。三角波也是週期性的波形，可以把其波形分為數個相位再對應到輸出振幅，就電路設計的觀念而言，利三角波來做轉換時，只需利用一個多工器來做相位振幅轉換，而不用使用到唯讀記憶體 (ROM)，可大大降低電路的複雜度，並且降低面積。

本論文針對所提出之架構做抖動之分析，並利用混合訊號之系統模擬，可達到快速預測輸出抖動；本架構之主要電路已用TSMC 0.18μm做設計及佈局，並利用FPGA及DAC做一系統原型，用示波器量測其輸出經降頻後之圖素速率時脈抖動，模擬及量測結果皆說明此架構之可行性。

In a LCD system, a frequency synthesizer with high multiplying ratio
is required to sample the analog RGB data from graphic card on PC.
The reference clock is a jittered clock, HSYNC. Since the RGB data
is phase aligned with the HSYNC, the synthesized pixel rate clock
should track the timing variation of the HSYNC.

Existing closed loop topologies of frequency synthesizers are not
able to track the variation of the HSYNC very fast due to their loop
bandwidths. An open loop architecture, whose core is a DDFS, is
proposed and analyzed in this thesis.

System simulation shows the feasibility of this architecture. Key
circuits were implemented using 0.18um CMOS technology. Measured
results of prototyping system show the jitter performance of the
modified pixel rate clock.

[1] F. Gardner, “Charge pump phase-lock loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849–1858, Nov 1980.

[2] Sheng Ye, Lars Jansson, and Ian Galton, “ A multiple-crystal interface PLL with VCO realignment to reduce phase noise, ” IEEE J. Solid-State Circuits, vol.37, pp.1795-1803, Dec. 2002.

[3] J. McNeill, “Jitter in ring oscillators, ” IEEE J. Solid-State Circuits, vol.32, pp. 870–879, June 1997.

[4] J. McNeill, Jitter in ring oscillators, Ph.D. dissertation, Boston University,1994.

[5] G. Chien and P. Gray, “A 900MHz local oscillator using a DLL-based
frequency multiplier technique for PCS applications,” in Dig. Tech. Papers,
IEEE ISSCC, Feb. 2000, pp. 202–203.

[6] G. Chien and P. R. Gray, “A900-MHz local oscillator using a DLL-based
frequency multiplier technique for PCS applications,” IEEE J. Solid-
State Circuits, vol. 35, pp. 1996–1999, Dec. 2000.

[7] Horng-Der Chang, “Hybrid phase locked loop, ” USA Patent 6686784.

[8] J. Tierney, C. M. Rader, and B. Gold, “A digital frequency synthesizer,” IEEE Trans. Audio Electroacoust., vol. AU-19, pp. 48–57, Mar. 1971.

[9] Jouko Vankka, “Direct digital synthesizer: theory, design and applications, ” Ph.D. dissertation, Helsinki University,2000.

[10] VESA and industry standards and guidelines for computer display monitor timing, Version 1.0, Revision 0.8, 1998.

[11] A. V. Bosch, et al, “A 10-bit 1-Gsample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, March 2001, pp. 315-324.

[12] Hiroyuki Kohno, Yasuyuki Nakamura, Atsuhito Kondo, Hiroyuki Amishiro, Takahiro Miki, and Keisuke Okada, “A 350-MS/s 3.3 V 8-bit CMOS D/A Converter Using a Delayed Driving Scheme,” Custom Integrated Circuits Conference, 1995, Proceedings of the IEEE 1995 , pages: 211 -214, 1-4 May 1995.

[13] B. D. Yang, J. H. Choi, S. H. Han, L. S. Kim, and H. K. Yu, “An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/A converter, ” IEEE J. Solid-State Circuits, vol.39, pp. 761–774, May 2004.

[14] L. K. Tan, E. W. Roth, G. E. Yee, and H. Samueli, “An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8μm CMOS, ” IEEE J. Solid-State Circuits, vol.30, pp. 1463–1473, Dec. 1995.

[15] A. G. M. Strollo, D. De Caro, and N. Petra, “A 630MHz, 76mW direct digital frequency synthesizer using advanced ROM compression technique,” IEEE J. Solid-State Circuits, vol.42, pp.350–360, Feb. 2007.

[16] D. E. Calbaza, and Y. Savaria, “A direct digital period synthesis circuit,” IEEE J. Solid-State Circuits, vol.37, pp.1039–1045, Aug. 2002.

[17] F. F. Dai, W. Ni, S. Yin, and R. C. Jaeger, “A direct digital frequency synthesizer with fourth-order phase domain △∑ noise shaper and 12-bit current steering DAC, ” IEEE J. Solid-State Circuits, vol.41, pp.839–850, Apr. 2006.

[18] D. De Caro, and A. G. M. Strollo, “High-performance direct digital frequency synthesizer in 0.25 μm CMOS using dual-slope approximation,” IEEE J. Solid-State Circuits, vol.40, pp.2220–2227, Nov. 2005.

[19] Sterling Smith, “High resolution digital controlled oscillator,” USA Patent 6714084.

[20] Lebouleux, “Method and system for kow power, low jitter, wide range, self-adaptive multi-frequency phase locked loop,” USA Patent 6693496.

[21] B. Razavi, Principles of Data Conversion System Design. New York: IEEE Press, 1995.

[22] B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw-Hill, 2001.

[23] P. E. Allen, and D. R. Holberg, CMOS Analog Circuit Design. Oxford, 2002.

[24] D. Calbaza and Y. Savaria, “Jitter model of DDS clock generators,” in Proc. ISCAS, vol. 1, 1999, pp. 1–4.

[25] J. Vankka, M. Waltari, M. Kosunen, and K. Halonen, “A direct digital synthesizer with an on chip D/A converter,” IEEE J. Solid-State Circuits, vol. 33, pp. 218–227, Feb. 1998.

[26] D. Calbaza, and Y. Savaria, “Direct digital frequency synthesis of low-jitter clocks,” IEEE J. Solid-State Circuits, vol. 36, pp. 570–572, Mar. 2001.

[27] C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6mm ,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948–1958,Dec. 1998.