以電路結構機率分析之智慧型亂數驗證向量產生器

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研究生：	郭育旻 Yu-Min Kuo
論文名稱：	以電路結構機率分析之智慧型亂數驗證向量產生器 Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure
指導教授：	張世杰 Shih-Chieh Chang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2004
畢業學年度：	92
語文別：	英文
論文頁數：	35
中文關鍵詞：	機率、亂數向量產生器、亂數模擬、偏向
外文關鍵詞：	probability, Random vector generator, Random simulation, Biased
相關次數：	點閱：2 下載：0
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由於現在的設計的複雜度以指數方式成長，使得驗證成為流程上的瓶頸，佔整個設計流程中的百分之七十的付出，在眾多驗證的方法中，模擬仍然是通用且重要的方法。傳統上模擬是由設計者撰寫驗證程式，但隨著設計增大，這樣一來不僅需要花很多時間而且不易達到很高的涵蓋率。另一方面，在驗證程式中也許存在著一些錯誤，這也需要額外的付出來找到錯誤的所，在統計上，約有四分之三的錯誤是藉由亂數模擬而找到的。近年來亂數模擬變得越來越重要，最主要的理由是它可以自動化來產生大量的驗證向量，而且可以發現許多設計中難以發現的錯誤。一個有效率的亂數驗證向量產生器與輸入端的機率有著極為密切的關聯性，所以在我的碩士論文中提出一個新的驗證架構---以電路結構機率分析之智慧型亂數驗證向量產生器，首先我們先提出一個評量輸入端機率的方法，接下來再自動化地去分析電路的架構，將輸入端的機率用偏移亂數的方式，動態地產生驗證向量，來進行電路的驗證。針對組合邏輯電路提出了三種方法，並且能進一步應用於循序邏輯電路上，來得到與狀態相關聯的輸入機率。論文中使用狀態數和輸出組合數進行測量，經實驗後，我們發現所提出的方法確實是有效的，可以比單純沒變化的亂數方式，有更高的涵蓋率。

Design verification has become a bottleneck of modern designs and dominates the whole VLSI design process. Recently, simulation-based random verification has attracted a lot of interests due to its effectiveness in uncovering obscure bugs and due to its automation in generating large vectors. Designers are often required to provide the input probabilities while conducting the random verification. However, it is extremely difficult for designers to provide accurate input probabilities. In this thesis, we propose an algorithm that derives good input probabilities such that the design intent can be exercised effectively for functional verification. We conducted experiments on several combinational and sequential benchmark circuits. The experimental results are very promising.

Contents
List of Figures............................................4
List of Tables.............................................5
Chapter 1. Introduction....................................6
Chapter 2. Evaluation of Input Probabilities..............10
Chapter 3. Intelligent Random Vector Generator............13
    3.1 Weighted Method..............................13
    3.2 Refinement Method............................17
    3.3 Dynamic Method...............................23
Chapter 4. Extension to Sequential Circuits...............27
Chapter 5. Experimental Results...........................30
Chapter 6. Conclusions....................................34
References................................................35

List of Figures
Figure 1: Example of uniform random simulation.............8
Figure 2: Example of biased random simulation..............8
Figure 3: Example with strong correlation.................12
Figure 4: Example with a simple tree structure............14
Figure 5: Backward propagation of probability.............15
Figure 6: Pseudo code of the weighted method..............16
Figure 7: Disadvantage of weighted method by averaging probabilities.............................................17
Figure 8: The refinement rules for AND and OR gates.......18
Figure 9: Single path from output to input................19
Figure 10: A node with multiple paths.....................20
Figure 11: Probabilities after refinement.................21
Figure 12: Pseudo code of the refinement method...........22
Figure 13: Probabilities after refinement.................24
Figure 14: Back propagate probabilities from outputs when a is 0......................................................25
Figure 15: Back propagate probabilities from outputs when a is 0 and b is 0...........................................26
Figure 16: Pseudo code of the dynamic method..............26
Figure 17: Example with an input-noncontrollable state variable..................................................28
Figure 18: Pseudo code for handling sequential circuits...29

List of Tables
Table 1: Experimental results of combinational circuits...32
Table 2: Experimental results of sequential circuits......33

                                

[1] Ken Albin , “Nuts and Bolts of Core and SoC Verification,” In Proc. of Design Automation Conference, 2001, June 2001.
[2] P. Faye, E. Cerny, and P. Pownall, “Improved Design Verification by Random Simulation Guided by Genetic Algorithms,” In Proc. of IEEE/IFIP World Computer Congress 2000, Int'l Conf. On Chip Design Automation (ICDA2000), page 2000.
[3] M. Kantrowitz, L.M. Noack, “Functional Verification of a Multiple-issue, Pipelined, Superscalar Alpha Processor – the Alpha 21164 CPU Chip,” In Digital Technical Journal, Vol. 7 No.1 Fall 1995.
[4] Yossi Levhari, “Verification of the PalmDSPCore Using Pseudo Random Techniques,” http://www. veri-sure.com/thesiss.html
[5] Tasiran, S., Fallah, F., Chinnery, D.G., Weber, S.J., and Keutzer, K. “A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage,” In Proceedings of 2001 Inter- national Conference on Computer Design (ICCD 2001), pages 82-88, 2001.
[6] System Science, Inc. (Synopsys, Inc.), “The VERA verification system,” http://www.systems.com/product/vera.
[7] Verisity Design, Inc., “Spec-man: Spec-based approach to automate functional verification,” http://www.verisity.com.

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