三維異質整合 (Heterogeneous integration) 是一個新興的研究方向，透過整合不同的製程技術可以帶來許多優勢，例如減少成本、增加性能等。由於這個全新的領域誕生，傳統的設計方法面臨困境。在分區領域，從傳統的單一平面，到三維的架構有許多新的挑戰產生。如何在滿足使用者制定的條件下可以獲得最小成本是我們所要解決的問題。在實際執行時的兩種條件: 反應時間 (Response time) 與吞吐量 (Throughput)，是我們對於一個應用最直接的衡量標準。在這篇論文中，我們探討在上述兩種條件下，我們如何透過啟發式演算法來得到接近最佳解的成果，並且分析我們如何得到這些結果。

3D heterogeneous integration is an emerging research direction,through the integration of different process technologies can bring many advantages, such as reducing costs and increasing performance. As this new field was born, traditional design methods faced difficulties. In partitioning, many new challenges arise from the traditional single plane to the three-dimensional architecture. How to obtain the minimum cost under the conditions specified by the user is the problem we want to solve. Two conditions during actual execution: response time and throughput, are our most direct measurement criteria for an application. In this paper, we explore how we use heuristic algorithms to get close to the optimal solution under the above two conditions and analyze how we get these results.

[1] C. M. Fiduccia and R. M. Mattheyses, “A linear-time heuristic for improving network
partitions,” in Proceedings of the 19th Design Automation Conference, DAC ’82, p. 175–
181, IEEE Press, 1982.
[2] B. W. Kernighan and S. Lin, “An efficient heuristic procedure for partitioning graphs,”
The Bell System Technical Journal, vol. 49, no. 2, pp. 291–307, 1970.
[3] C. Ababei, S. Navaratnasothie, K. Bazargan, and G. Karypis, “Multi-objective circuit
partitioning for cutsize and path-based delay minimization,” in IEEE/ACM International
Conference on Computer Aided Design, 2002. ICCAD 2002., pp. 181–185, Nov 2002.
[4] M. Shih, E. Kuh, and R.-S. Tsay, “Performance-driven system partitioning on multichip modules,” in [1992] Proceedings 29th ACM/IEEE Design Automation Conference,
pp. 53–56, 1992.
[5] N. Meitei, K. Baishnab, and G. Trivedi, “3d-ic partitioning method based on genetic algorithm,” IET Circuits Devices Systems, vol. 14, pp. 1104–1109, 10 2020.
[6] S. Banerjee, S. Majumder, and B. B. Bhattacharya, “A graph-based 3d ic partitioning
technique,” in 2014 IEEE Computer Society Annual Symposium on VLSI, pp. 613–618,
2014.
[7] D. P. Sivaranjani and G. Srividhya, “3D IC PARTITIONING BY USING FAST
FORCE DIRECTED SIMULATED ANNEALING ALGORITHM FOR REDUCING
THROUGH-SILICON VIAS,” International Journal of Advanced Trends in Engineering
and Technology, vol. 1, pp. 6–11, Mar. 2017.
[8] S. Sawicki, R. Hentschke, M. Johann, and R. Reis, “An algorithm for i/o pins partitioning
targeting 3d vlsi integrated circuits,” pp. 699 – 703, 09 2006.
[9] I. H.-R. Jiang, “Generic integer linear programming formulation for 3d ic partitioning,”
in 2009 IEEE International SOC Conference (SOCC), pp. 321–324, 2009.
[10] S. Ghorui, S. Banerjee, and S. Majumder, “A deterministic multi-layered partitioning tool
for wire-length reduction of monolithic 3d-ic,” in 2019 IEEE 26th International Conference on High Performance Computing, Data, and Analytics (HiPC), pp. 44–51, 2019.
[11] J. Hertz, “Scaling down to 3nm will require advances in fabrication technology,” 2021.
[12] MediaTek, “Mediatek dimensity 9000,” 2021.
[13] T. Li, J. Hou, J. Yan, R. Liu, H. Yang, and Z. Sun, “Chiplet heterogeneous integration
technology—status and challenges,” Electronics, vol. 9, no. 4, 2020.
[14] J. Knechtel, J. Lienig, and I. A. Elfadel, “Multi-objective 3d floorplanning with integrated
voltage assignment,” ACM Transactions on Design Automation of Electronic Systems,
vol. 23, 11 2017.
[15] J. Siegel, D. Erb, and S. Sarma, “Algorithms and architectures: A case study in when,
where and how to connect vehicles,” IEEE Transactions on Intelligent Transportation
Systems Magazine, vol. 10, 01 2017.
[16] L. Xu, “Context aware traffic identification kit (trick) for network selection in future hetnets/5g networks,” pp. 1–5, 05 2017.
[17] M. A. Ahmed and M. Chrzanowska-Jeske, “Delay and power optimization with tsv-aware
3d floorplanning,” in Fifteenth International Symposium on Quality Electronic Design,
pp. 189–196, 2014.