序言 I 摘要 II CONTENTS III FIGURES VI CHAPTER1 MOTIVATION AND INTRODUCTION 1 1.1 INTRODUCTION 2 1.2 OUTLINE OF THIS PROPOSAL 3 CHAPTER2 FEATURES AND INNOVATION OF OUR DESIGN 4 2.1 INHERIT THE BENEFITS FROM LOAD-BALANCED BIRKHOFF-VON NEUMANN SWITCH 4 2.2 FOLDED ARCHITECTURE TO REDUCE CENTRALIZED VOQ BUFFER COMPLEXITY 4 2.3 SWITCHING LEVEL PARALLELISM TO RESTORE 100% THROUGHPUT 4 2.4 RELIEF OF ORIGINAL SHORT DISTANCE VARIATION CONSTRAINT 5 2.5 3-LEVEL HIERARCHY VOQ BUFFER DESIGN TO FIT PIPELINE TIMING BUDGET 5 2.6 ADDITIONAL RE-SEQUENCE BUFFER TO SIMPLIFY CELL REASSEMBLY 5 2.7 SYNCHRONIZATION PROTOCOL AND FAULT-TOLERANT SWITCH FABRIC TO PREVENT UNRECOVERABLE REASSEMBLY 6 2.8 PROTOTYPE CREATED BASED ON STANDARD ADVANCEDTCA PLATFORM 6 CHAPTER3 CHALLENGES AND DESIGN SOLUTIONS 7 3.1 PRELIMINARY 7 3.1.1 Cell Transmission Time 7 3.1.2 SERDES Channel Latency 9 3.2 CHALLENGES 11 3.2.1 Central VOQ Buffer Complexity Limits Scalability 11 3.2.2 Long Transmission Latency Limits Throughput 11 3.2.3 Synchronization Assumption Restrains Propagation Distance Variation 12 3.2.4 Traditional VOQ Buffer Management Requires Speedup 12 3.2.5 Out-of-Order Transmission Makes Reassembling Difficult 13 3.2.6 Faulty Linecard Makes Permanent Unrecoverable Reassembly 13 3.3.1 Folded Architecture Design 14 3.3.2 Switching Level Parallelism 17 3.3.3 Synchronization Analysis 20 3.3.4 VOQ Buffer Design 23 3.3.5 Re-sequence Buffer Design 29 3.3.6 Fault Tolerant Design 32 3.3.6.1 Linecard Synchronization Protocol Design 32 3.3.6.2 Fault-tolerant symmetric TDM switch 35 CHAPTER 4 SYSTEM ARCHITECTURE 42 4.1 ASSUMPTION 43 4.2 HARDWARE DESIGN 44 4.2.1 Linecard Blade Design 45 4.2.2 Switch Fabric Blade Design 47 4.2.3 Stand-alone switch integration 48 4.3 SYSTEM OPERATION 50 4.3.1 Ingress Process 50 4.3.2 First Stage Switch 51 4.3.3 VOQ Buffer 52 4.3.4 Second Stage Switch 53 4.3.5 Re-sequencing Buffer 54 4.3.6 Egress Process 55 CHAPTER 5 IMPLEMENTATION OF SWITCH, LINECARD AND I/O INTERFACE 57 5.1 MAIN ARCHITECTURE 57 5.2 LINE CARD DESIGN 59 5.2.1 Network Processor Simulator and CSIX Interface 60 5.2.2 Cell Writer and Cell Reader 61 5.2.3 Synchronous protocol 62 5.3 SWITCH DESIGN 63 5.3.1 Synchronous Protocol 64 5.3.2 Registration Manager 64 5.3.3 Switch Fabric & Switch Control Logic 66 5.3.4 FIFO Manager 71 5.4 SYNCHRONOUS PROTOCOL DESIGN 72 5.4.1 Finite State Machine 72 5.4.2 Cell Format for Sync Protocol 74 5.4.3 Sync Protocol Design for Linecard Side 76 5.4.4 Sync Protocol Design for Switch Side 77 5.4.5 Inject & Tap Module 78 5.5 SERDES INTERFACE 80 CHAPTER6 EXPERIMENT RESULT 82 6.1 ENVIRONMENT FOR EXPERIMENT AND INTRODUCTION TO TEST CASE 82 6.2 NETWORK PROCESSOR SIMULATOR 83 6.2.1 Queue Generator 83 6.2.2 Packet Generator 83 6.3 MODULES OF LINECARD SIDE 84 6.3.1 CSIX RX Interface 84 6.3.2 Cell Writer 84 6.3.3 Inject Module 86 6.3.4 Tap Module & Queue Command Generator 87 6.3.5 SERDES Detector 89 6.4 MODULES OF SWITCH SIDE 90 6.4.1 Registration Manager 90 6.4.2 Inject Module & Tap Module 91 6.4.3 SERDES Detector 91 6.4.4 FIFO Manager 93 6.4.5 STDM Controller & Loader 94 6.4.6 Sorting Network, STDM Switch and Restoration Network 94 6.5 AURORA CONTROLLER 98 CHAPTER 7 CONCLUSIONS 99 REFERENCE 100