在這份研究裡，為了支援室內雷達系統晶片的高頻時脈 1-4GHz 的範圍，我們以全數位鎖定延遲迴路倍頻器的電路系統，藉此來擴展可達成的最高操作頻率。依據 [12] 和 [13]，為了產生多個精準的相位，我們使用了一個創新的架構:我們利用週期訊號會持續重複的特性，對相位作精準的校正，使其能對對抗製程變異所帶來的誤差，並且在得到 8 個 1GHz 的相位之後，將這 8 個相位組先經過脈衝寬度的處裡，再藉由邏輯運算組合波型使其加速，最後將其責任區間修復回50%，成為最後我們想要的目標時脈。
根據電路布局圖的模擬結果顯示，我們所產生出的時脈與目標 4GHz 的頻率誤差僅不到 0.01% 、以及 7.48ps 的均方根抖動，面積與功耗分別為為0.104mm2和12.67mW。
整個實驗中有兩個特別困難的地方。第一個是在產生多相位的階段中，為了產生最少125ps的相位差，我們必須設計出一個能被精確地控制的可調延遲元件，然而125ps的延遲時間，對以90nm製程所設計的電路來說尚且太難，因此我們利用了週期訊號會持續重複的特性，藉由設計出1125ps的延遲來取得125ps的相位差，並達成目標。第二個困難之處，則是如何創造出其他可選擇的不同相位。以傳統的方法來說，將鎖定延遲迴路的輸出端和輸入端作相位上的比較，然後將其得到的延遲時間作平均的分配、需要幾個相位就分成幾等份，以此來得到不同的相位。然而這個方法卻不適用於我們的電路，因為會造成可調延遲元件所需覆蓋的延遲範圍上的負擔，因此我們採用了另一種新的相位分配方法，如此一來可調延遲元件便能完全覆蓋我們所需的延遲範圍。

In this work we try to extend the maximum operating frequency achievable by all-digital delay-locked loop (DLL) based frequency multiplication circuit to support a high-speed range of 1GHz to 4GHz, to be used by our in-house radar system on chip (SoC). This goal is achieved by an innovative architecture in which an 8 phases of 1GHz clock signals pre-generated using techniques proposed in [12] and [13] are combined to form the waveform of the final target clock signal.
Post-layout simulation result shows that the frequency error of the generated 4GHz clock signal is below 0.01% with a 7.48ps RMS-jitter, and the active area and the power consumption is 0.104mm2 and 12.67mW respectively.

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