簡易檢索 / 詳目顯示

研究生: 黃惠民
論文名稱: 超薄閘氧化層之多重軟崩潰對互補式金氧半邏輯閘的影響
Effect of Ultra-thin Gate Oxide Multiple Soft Breakdown on CMOS Logic Gates
指導教授: 金雅琴
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2005
畢業學年度: 93
語文別: 中文
論文頁數: 65
中文關鍵詞: 閘氧化層軟崩潰可靠性
外文關鍵詞: Gate Oxide, Soft Breakdown, Reliability
相關次數: 點閱:2下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 閘氧化層的微縮化是目前高效能金氧半場效電晶體製造技術的趨勢。在微縮化的過程中,觀察到一個漸進式的崩潰現象,使得氧化層的漏電流呈現出階梯狀的上升,此現象稱之為多重軟崩潰。所以閘氧化層微縮化的進展將被多重軟崩潰現象所侷限,是否能在產品操作生命期之內容許元件遭受多重軟崩潰的發生,已成為目前非常重要的一個研究課題。
    互補式金氧半反向器在數位電路上是最基本的組成元件。因此在本篇論文中,首先討論多重軟崩潰對互補式金氧半反向器特性上影響,然後利用實驗上的量測數據,將此崩潰特性模型化;藉由模擬方式,以邏輯閘電路,互補式金氧半環形震盪器為例,評估多重軟崩潰對電路功能上所造成的影響。


    The scaling of gate oxide leads to fabrication of high performance MOSFETs. When oxide scaling, however, a progressive breakdown phenomenon has been observed. This progressive breakdown event produces a stepping increase of oxide leakage current. This phenomenon is often refers to as Multi-SBD (Multiple Soft Breakdown). Therefore, gate oxide scaling can be limited by Multi-SBD occurring during device operation lifetime. Hence, it is essential to study the impact of multiple on soft breakdown.
    CMOS inverter is the most basic element of digital circuits. In this work, the impact of CMOS inverter by Multi-SBD has been investigated. The breakdown modeling proposed based on the physical measurement data can be used for determining how strongly gate oxide soft breakdown affects circuit operation. Such assessment is completed by simulation study on a CMOS ring oscillator operation after Multi-SBD occurs in the circuit.

    中文摘要 英文摘要 誌謝 目錄 附圖目錄 第1章 緒論...........................1 1.1 動機 1.2 論文架構 第2章 閘氧化層可靠性之回顧...........3 2.1 崩潰模型 2.2 文獻摘要 第3章 量測系統設置與實驗設計.........7 3.1 量測系統設置 3.2 實驗設計 第4章 實驗結果與討論.................10 4.1 多重軟崩潰特性及理論 4.2 電壓轉換特性偏移 4.3 待機功率消耗 4.4 崩潰點發生位置 第5章 崩潰模型之建立.................16 5.1 元件模型校正 5.2 崩潰特性模型化 第6章 電路模擬及討論.................20 6.1 電路結構及模擬條件 6.2 模擬結果討論 6.2.1 電壓波形 6.2.2 瞬時功率消耗 6.2.3 案例研究:隨機崩潰 第7章 結論...........................25 參考文獻...............................27 附圖...................................29

    [1] J.W. McPherson, V.K. Reddy, H.C. Mogul, "Field-enhanced Si-Si bond-breakage mechanism for time-dependent dielectric breakdown in thin-film SiO2 dielectrics" in AIP-APL, 1997, 71(8), pp.1101-1103.
    [2] J.W. McPherson, H.C. Mogul, "Disturbed bonding states in SiO2 thin-films and their impact on time-dependent dielectric breakdown" in IEEE-IRPS, 1998, pp.47-56.
    [3] K.P. Cheung, "A physics-based, unified gate-oxide breakdown model." in IEEE-IEDM, 1999, pp.719-722.
    [4] K.F. Schuegraf, C. Hu, "Hole injection oxide breakdown model for very low voltage lifetime extrapolation" in IEEE-IRPS, 1993, pp.7-12.
    [5] R. Degraeve, G. Groeseneken, R. Bellens, M. Depas, H.E. Maes, "A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides" in IEEE-IEDM, 1995, pp.863-866.
    [6] J.H. Stathis, "Percolation models for gate oxide breakdown" in AIP-JAP, 1999, 86(10), pp.5757-5766.
    [7] J. Suñé, I. Placencia, N. Barniol, E. Farrés, F. Martín, X. Aymerich, "On the breakdown statistics of very thin SiO2 films" in Thin Solid Films, 1990, 185, pp.347-362.
    [8] W. Lai, J. Suñé, E. Wu, E. Nowak, "Impact of stress induced leakage current on power-consumption in ultra-thin gate oxides" in IEEE-IRPS, 2004, pp.102-109.
    [9] E. Wu, E. Nowak, W. Lai, "Off-state mode TDDB reliability for ultra-thin gate oxides: new methodology and the impact of oxide thickness scaling" in IEEE-IRPS, 2004, pp.84-94.
    [10] B.J. Cheek, N. Stutzke, S. Kumar, R.J. Baker, A.J. Moll, W.B. Knowlton, "Investigation of circuit-level oxide degradation and its effect on CMOS inverter operation and MOSFET characteristics" in IEEE-IRPS, 2004, pp.110-116.
    [11] T. Pompl, H. Wurzer, M. Kerber, R.C.W. Wilkins, I. Eisele, "Influence of soft breakdown on NMOSFET device characteristics" in IEEE-IRPS, 1999, pp.82-87.
    [12] E. Wu, E. Nowak, J. Aitken, W. Abadeer, L.K. Han, S. Lo, "Structural dependence of dielectric breakdown in ultra-thin gate oxides and its relationship to soft breakdown modes and device failure" in IEEE-IEDM, 1998, pp.187-190.
    [13] R. Degraeve, B. Kaczer,A. De Keersgieter, G. Groeseneken, "Relation between breakdown mode and breakdown location in short channel NMOSFETs and its impact on reliability specifications" in IEEE-IRPS, 2001, pp.360-366.
    [14] S. Lombardo, J.H. Stathis, B.P. Linder, "Breakdown transients in ultra-thin gate oxides: transition in the degradation rate" in IEEE-SISC, 2002.
    [15] T. Hosoi, P.L Ré, Y. Kamakura, K. Taniguchi, "A new model of time evolution of gate leakage current after soft breakdown in ultra-thin gate oxides" in IEEE-IEDM, 2002, pp.155-158.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 本全文未授權公開 (國家圖書館:臺灣博碩士論文系統)
    QR CODE