簡易檢索 / 詳目顯示

研究生: 王國榮
論文名稱: 200V 溝渠式橫向雙擴散金氧半場效電晶體之設計
The Design of 200V Trench LDMOSFET
指導教授: 龔正
J. Gong
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2005
畢業學年度: 93
語文別: 中文
論文頁數: 68
中文關鍵詞: 功率元件降低表面電場溝渠
相關次數: 點閱:2下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 本篇論文所研究的功率元件為橫向式的DMOSFET,其優點在於可以整合在平面製程上。因為傳統的LDMOSFET具有高導通電阻和大面積的缺點,本篇論文採用最近提出的新方法來設計元件—Trench LDMOSFET,利用此結構可以有效降低導通電阻以及減少元件面積。
    本篇論文的設計目標是要能應用在PDP驅動電路,期望設計出一顆應用在PDP中的200V功率元件。利用Tsuprem4和Medici等模擬軟體,分別模擬Trench LDMOSFET和RESURF LDMOS的結構和電性,最後再來討論比較。


    The power device in this thesis is Lateral DMOSFET (Double-diffusion MOSFET), and it’s easily to integrated into planar process. Because conventional LDMOSFET has shortages of large on-resistance and cell pitch , we choose Trench LDMOSFET that is recently introduced to improve these characteristics.
    The subject for this thesis would be the design of a 200V power devices,it could be applied to PDP(Plasma Display Panel) driver IC.In this work We use simulation tools like Tsuprem4 and Medici to simulate the electric characteristics of Trench LDMOSFET and RESURF LDMOSFET. Finally,the results of simulation are discussed.

    第一章 前言 1 第二章 原理回顧 3 2.1 LDMOSFET結構與操作原理 3 2.2 功率元件的崩潰機制 4 2.3 RESURF(降低表面電場)原理 9 2.4 LDMOSFET的導通電阻 14 第三章 Trench LDMOSFET的優點 18 3.1 RESURF LDMOSFET的缺點 18 3.2 二氧化矽溝渠對LDMOSFET的改善 22 第四章 Trench LDMOSFET最佳化設計 28 4.1 參數定義 28 4.2 Trench LDMOSFET的製程步驟 32 4.3 Trench LDMOSFET的結構分析 37 4.4 Trench LDMOSFET的設計 55 4.5 Trench LDMOSFET和RESURF LDMOSFET的比較 61 第五章 結論 64 參考文獻    65

    [1] Tsui, P.G.Y.; Gilbert, P.V.; Shih Wei Sun, “Integration of power LDMOS into a low-voltage 0.5 μm BiCMOS technology”, IEDM Tech. Dig., pp.27-30 ,1992
    [2] Hidalgo, S.; Fernandez, J.; Godignon, P.; Rebollo, J.; Millan, J. , “Power lateral DMOS transistor test structures”, ICMTS 1993 ,
    pp. 33 -38
    [3] Donald A. Neamen, Semiconductor Physics & Devices, Second Edition, Copyright 1997.1992 by McGraw-Hill Inc
    [4] B. J. Baliga, Power Semiconductor Devices, Copyright 1996 by PWS
    [5] J. A. Appeals, and H. M. J. Vaes, “High-voltage thin layer devices (RESURF devices)”, IEDM Tech. Dig., pp. 238-239, 1979
    [6] A. Ludikhuize, “A review of RESURF technology”, ISPSD '00, pp. 11-18
    [7] Zahir Parpia, and C. Andre T. Salama, “Optimization of RESURF LDMOS transistors: an analytical approach”, IEEE Electron Device, Vol. ED-37, No. 3, pp. 789-795
    [8] Merchant, S.; Arnold, E.; Baumgart, H.; Egloff, R.; Letavic, T.; Mukherjee, S.; Pein, H. , “Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors”, ISPSD '93, pp.124-128
    [9] Zitouni, M.; Morancho, F.; Rossel, P.; Tranduc, H.; Buxo, J.; Pages, I. , “A new concept for the lateral DMOS transistor for smart power IC's”, ISPSD '99, pp.73-76
    [10] Yuanzheng Zhu; Liang, Y.C.; Shuming Xu; Pang-Dow Foo; Sin, J.K.O “Folded gate LDMOS transistor with low on-resistance and high transconductance”, Electron Devices, IEEE Transactions on, Volume 48 , pp.2917 – 2928 ,2001
    [11] Baba, Y.; Yanagiya, S.; Koshino, Y.; Udo, Y, “High voltage trench
    drain LDMOS-FET using SOI wafer”, ISPSD '94 , pp.183 - 186
    [12] AVANT! TSUPREM-4, Two-Dimensional Process Simulation Program,Version-2000.4.0
    [13] AVANT! MEDICI, Two-Dimensional Device Simulation Program, Version-2000.4.0
    [14] Der-Gao Lin; Tu, S.L.; Yee-Chaung See; Pak Tam, “A novel LDMOS structure with a step gate oxide” , IEDM, pp.963 – 966 ,1995
    [15] Hossain, Z.; Ishigwo, T.; Tu, L.; Corleto, H.; Kuramae, F.; Nair, R, “Field-plate effects on the breakdown voltage of an integrated high-voltage LDMOS transistor”, ISPSD '04, pp.237 - 240
    [16] David K. Cheng, Field and Wave Electromagnetics 2/e , Copyright 1996 by Addison-Wesley
    [17] Sze, S.M, Semiconductor Devices Physics and Technology, Copyright 1997 by John Wiley & Sons Inc
    [18] M.F. Lee, “The Simulation and Design of 200V Lateral Semiconductor Power Devices”, Thesis of NTHU, ENE. Master, 2000
    [19] Sang-Koo Chung, “An analytical model for breakdown voltage of surface implanted SOI RESURF LDMOS”, Electron Devices, IEEE Transactions on, Volume 47, pp. 1006 – 1009 ,2000
    [20] Lee, S.K.; Kim, C.J.; Kim, J.H.; Choi, Y.C.; Kang, H.S.; Song, C.S, “Optimization of safe-operating-area using two peaks of body-current in submicron LDMOS transistors”, ISPSD '01, pp. 287 - 290

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 本全文未授權公開 (國家圖書館:臺灣博碩士論文系統)
    QR CODE