由於掃瞄鏈 (scan chain)的故障佔據了良率損失 (yield loss)上的很大比例，所以在掃瞄鏈的診斷已經成為當今非常關鍵的議題。在這篇論文中，針對掃瞄鏈的診斷我們提出了掃瞄鏈上排序重置的方法來改善掃瞄鏈錯誤的發生。這個掃瞄鏈上排序重置的方法使用雙邊配對 (bipartite matching)演算法來減少可能發生錯誤的掃瞄正反器 (scan flip flop)的範圍。接著使用模擬退火 (simulated annealing)演算法來降低由於重置掃瞄正反器排序所需付出的代價。實驗結果顯示我們所提出的方法能夠有效的減少可能發生錯誤的掃瞄正反器的範圍。

Because scan chain failure is responsible for a large percentage of yield loss, scan chain diagnosis has become a critical issue in modern technology. In this paper, we present a scan chain reordering algorithm to improve scan chain fault diagnosis resolution. The ordering of scan cells is performed to decrease the range of suspect faulty scan cells by a bipartite matching reordering algorithm. Then simulated annealing algorithm is used to refine the wire length overhead. The experimental results show that our approach can effectively reduce the number of suspect scan cells for most cases of ITC'99 benchmarks.

S. Kasapi, J. Liao, B. Cory, ``Laser Voltage Imaging (LVI) for ATPG Scan Chain Diagnosis on 40nm CMOS,'' LSI Testing Symposium, Osaka, Japan, November 2010.

J. Schafer, F. Policastri, R. Mcnulty, ``Partner SRLs for Improved Shift Register Diagnostics,'' Proc. VTS, pp. 198-201, 1992

S. Kundu, ``Diagnosing Scan Chain Faults,'' IEEE TVLSI, Vol. 2, No.4, pp. 512-516, December 1994.

S. Edirisooriya, G. Edirisooriya, ``Diagnosis of Scan Path
Failures,'', Proc. VTS, pp. 250-255, 1995.

K. De, A. Gunda, ``Failure Analysis for Full-Scan ircuits'',
Proc. ITC, pp. 636-645, Mar. 1995.

S. Narayananan, A. Das, ``An Efficient Scheme to Diagnose Scan Chains,'' Proc. ITC, pp. 704-713, 1997.

Y.Wu, ``Diagnosis of Scan Chain Failures,'', Proc. Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 217-222-10, 1998.

P. Song, F. Motika, D. Knebel, R. Rizzolo, M. Kusko, J. Lee and M. McManus, ``Diagnostic techniques for the IBM S/390 600MHz G5 Microprocessor'', Proc. ITC, pp. 1073-1082, 1999.

J. Hirase, N. Shindou and K. Akahori, ``Scan Chain Diagnosis using IDDQ Current Measurement'', Proc. ATS, pp. 153-157, 1999.

K. Stanley, "High Accuracy Flush and Scan Software Diagnostic," Proc. IEEE YOT 2000, Oct. 2000.

R. Guo, S. Venkataraman, ``A Technique For Fault Diagnosis of
Defects in Scan Chains,'' ITC, pp. 268-277, 2001.

Y. Huang, W.-T. Cheng, S.M. Reddy, C.-J. Hsieh, Y.-T.
Hung,``Statistical Diagnosis for Intermittent Scan Chain Hold Time Fault'', ITC, pp.319-328, 2003

J. S. Yang, S. Huang, ``Quick Scan Chain Diagnosis Using Signal Profiling,'' ICCD, 2004

Y. Huang, W.T. Cheng and G. Crowell. ``Using Fault Model Relaxation to Diagnose Real Scan Chain Defects,'' ASP-DAC , pp. 1176-1179 ,2005

A. Crouch,``Debugging and Diagnosing Scan Chains.'', EDFAS, pp. 16-24, Feb. 2005.

J. Li, ``Diagnosis of Single Stuck-at Faults and Multiple Timing Faults in Scan Chains'', IEEE TVLSI, Vol.13, No.6, pp.
708-718, June 2005

J. Li,``Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains'', IEEE TC, Vol. 54, No. 11. pp 1467-1472, Nov. 2005

C,L, Kong, M.R. Islam, ``Diagnosis of Multiple Scan Chain Faults,'' International Symposium for Testing and Failure Analysis, pp.510-516. November 2005.

R. Guo, S. Venkataraman, ``An algorithmic technique for diagnosis of faulty scan chains'', IEEE Trans. on CAD, pp. 1861-1868, Sept.

Y. Huang, W.-T. Cheng, N. Tamarapalli, J. Rajski, R. Klimgerberg, W. Hsu and Y.-S. Chen, ``Diagnosis with Limited Failure Information'', ITC, paper 22.2, 2006

F. Motika, P. Nigh, P. Song, ``Stuck-at fault scan chain diagnostic method'' US Pat 7010735, July, 2003.

A. Anderson, et. al., ``Method, apparatus, and computer program product for implementing deterministic based broken scan chain diagnostics'', US Pat 20050229057, Oct. 2005

R. Guo, Y. Huang, W.-T Cheng, ``A complete test set to diagnose scan chain failures,'', ITC, pp.1-10, Oct. 2007

``Design Compiler'', Synopsys.

``SoC Encounter'', Cadence.