白金奈米晶粒於金屬－氧化物－半導體結構中對非揮發性懸浮閘極記憶體應用之研究

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研究生：	曾駿逸 Jiun-Yi Tseng
論文名稱：	白金奈米晶粒於金屬－氧化物－半導體結構中對非揮發性懸浮閘極記憶體應用之研究 A Study of Pt Nanocrystals in Metal-Oxide-Semiconductor Structures for Nonvolatile Floating Gate Memory Applications
指導教授：	吳泰伯 Tai-Bor Wu
口試委員:
學位類別：	博士 Doctor
系所名稱：	工學院 - 材料科學工程學系 Materials Science and Engineering
論文出版年：	2004
畢業學年度：	93
語文別：	英文
論文頁數：	167
中文關鍵詞：	非揮發性記憶體、白金奈米晶粒、懸浮閘極
外文關鍵詞：	non-volatile memory, Pt nanocrystal, floating gate
相關次數：	點閱：3 下載：0
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摘要
存在於金屬－氧化物－半導體(MOS)結構中的白金奈米晶粒(Pt nanocrystal) 對於非揮發性(nonvolatile)懸浮閘極(floating gate)記憶體的應用在本論文中有詳細地探討。為了製造此種新型奈米尺寸的非揮發性記憶體,一種新穎又簡單且具有再現性的製程方法(利用白金氧化物(PtOx)在高溫的還原特性)已成功地被開發出來。利用此製程所形成的白金奈米晶粒不但具有均勻分佈於基材(SiO2)且擁有良好的絕緣等特性;此外白金奈米晶粒之尺寸集中於2-3 nm且同時擁有極高的奈米晶粒密度約為2.16*1012 cm-2完全符合此新型奈米尺寸非揮發性記憶體的要求。在本研究中,由於電子(electron)或電洞(hole)儲存於白金奈米晶粒所造成電容-電壓曲線(C-V curve)的遲滯(hysteresis)現象清楚地被觀察到,亦實際證明此新型奈米記憶體對於非揮發性元件應用之可行性。同時在本研究中,我們也發現儲存電荷的機制主要有兩種;其一為藉由基板注入(sbustrate injection),另一個機制乃是藉由gate oxid內部缺陷電荷注入(defect injection)所造成。這兩種機制同時存在且相互競爭,在較薄的tunnel oxide下,基板注入變成主要的儲存電荷機制,反之則為缺陷電荷注入。而在儲存電荷(charge storage)與保存電荷(retention)的記憶特性方面,藉由基板注入的機制相較於缺陷電荷注入的機制穩定且有效率。在本研究中,我們亦探討不同真空熱處理時間對此非揮發性記憶元件之特性的影響。研究中發現,較長的熱處理時間(≧ 25 min)對於gate oxide內部缺陷的回復(recovery)與促進白金奈米晶粒良好的絕緣性有很大的幫助,並進而改善且降低側向漏電(lateral charge loss)與缺陷電荷注入(defect injection)的效應。因此較長時間熱處理的元件擁有較好的儲存電荷與保存電荷之記憶特性。再者,根據電導-電壓曲線(G-V curve)特性的結果可知,由於庫倫阻塞效應(Coulomb blockade effect)所造成的室溫巨觀單電子傳輸(macroscopic single-electron transfer)行為存在於此金屬－氧化物－半導體結構中的白金奈米晶粒。

Abstract
The nonvolatile memory characteristics of metal-oxide-semiconductor structures containing Pt nanocrystals in SiO2 gate oxide were studied. In this work, a novel, simple and reliable self-assembly process of Pt nanocrystals formation from the reduction of an ultrathin PtOx layer embedded in SiO2 matrix is developed successfully, which is fully compatible with Si technology nowadays. The self-assembled array of uniformly-dispersed and well-isolated Pt nanocrystals with the high spatial density (~2.16×1012 cm-2) and a narrow size distribution in the range of 2-3 nm was obtained by vacuum annealing at 425 ℃ for 25 min. A large hysteresis loop was found in the capacitance-voltage (C-V) relation indicating this significant memory effect. However, two different charge storage mechanisms were found for the Pt nanocrystals in the devices with different tunnel oxide thickness. One is denoted by the counterclockwise hysteresis resulting from substrate injection for the devices made with a thin tunnel oxide layer of 2.5~5.0 nm thick, and the other is characterized by the clockwise hysteresis attributed to the defect injection from the overlaid sputtered gate oxide for the devices having a tunnel oxide layer of 7.5 nm thick. The two mechanisms, substrate injection and defect injection, coexist at the same time but compete with each other. For tunnel oxide being thick enough (≧ 7.5 nm), the substrate injection would be significantly suppressed, and thus the defect injection becomes dominant. A model of defect injection is proposed to explain the clockwise hysteresis. The relatively stable memory characteristics of Pt nanocrystals resulting from substrate injection were also demonstrated. In Chapter 6, the effects of annealing time on the microstructure and electrical characteristics of the self-assembled Pt nanocrystals in SiO2 matrix are clear and significant. For a long enough annealing time, not only the Pt nanocrystals are well isolated and uniformly dispersed, but also the defects in the sputtered oxide are recovered. The superior charge storage and retention characteristics can be obtained due to the small lateral charge loss and the suppression of defect injection. Moreover, according to the gate-voltage dependence of charge storage and the result of the conductance-voltage (G-V) measurement, the macroscopic single-electron transfer due to the Coulomb blockade effect in the MOS device with embedded Pt nanocrystals is successfully demonstrated at room temperature in this research.

Contents
ABSTRACT                                                        Ⅰ
摘要                                                               Ⅲ
誌謝                                                               Ⅴ
CONTENTS                                                        Ⅶ
LIST OF TABLE                                                  ⅩⅡ
LIST OF FIGURE                                                 ⅩⅢ
CHAPTER 1 Introduction                                             1
1.1 Prelude                                                           1
1.1.1   A Severe Gap between Si-ULSI and Nanodevices                  1
1.1.2   Three Phases in Development of Silicon Nanodevices               2
1.1.3   The Problem with Floating Gate Non-volatile Memories             4
1.2 Motivation and Objectives of Research                                 5
CHAPTER 2 Literature Review                                       10
2.1 Introduction to Memories                                           10
   2.1.1   Semiconductor Memories                                    10
   2.1.2   Mechanical memories (Mass-Storage memories)                  11
2.2 Overview of Semiconductor Memories                                12
   2.2.1   Performance Considerations                                  12
   2.2.2   Non-volatile Semiconductor Memories                         14
2.3 Nanocrystal Memories                                             16
   2.3.1   Overview of Nanocrystal / Nanodot memories                    16
   2.3.2   Theory of Silicon Nanocrystals Devices                         17
   2.3.3   Metal Nanocrystal Memories                                 19
   2.3.4   Alternative Nanocrystal Devices                               20
          2.3.4.1   Double Stacked Nanodots                           20
          2.3.4.2   Silicon Nanocrystals with Oxide-Nitride Dielectrics       21
2.4 Single Electron Memories                                           22
2.5 Metal-Oxide-Semiconductor Devices                                  25
   2.5.1   Surface Potential: Accumulation, Depletion, and Inversion          25
   2.5.2   Shift of Flat-Band Voltage                                    28
Chapter 3 Experimental Procedure                                     38
3.1 Devices Fabrication                                                38
3.1.1   RCA Clean                                                38
3.1.2   Back-side Ion Implantation                                   39
3.1.3   Dry Thermal Oxidation                                      39
3.1.4   PtOx Ultrathin Film and Gate Oxide Deposition                  40
3.1.5   Pt Nanocrystal Formation                                    41
3.1.6   Metallization                                              41
3.2 Analysis and Measurement                                          42
   3.2.1   Binding Energy Analysis                                     42
   3.2.2   Microstructure Observation                                   42
   3.2.3   Electrical Measurement                                      42
Chapter 4 Effect of Different Tunnel Oxide Thickness on MOS Device with Embedded Pt Nanocrystals                                           49
4.1 Introduction                                                      49
4.2 Experimental                                                     51
4.3 Results and Discussion                                             52
4.3.1   Self-Assembled Pt Nanocrystals                               52
4.3.2 Analysis of X-ray Photoelectron Spectroscopy                      53
4.3.3 Charge Storage Effect (Memory Effect) in Capacitance-Voltage Relations 54
4.3.4 Current-Voltage Characteristics                                  58
4.3.5 Effect of Gate Voltage on Flat-Band Voltage (Vfb)                   58
4.3.6 Effect of Measurement Frequency on Flat-Band Voltage              59
4.3.7 Retention Characteristic                                        59
4.4 Conclusions                                                      60
Chapter 5 Effect of Different Gate Oxide Thickness on MOS Device with 7.5 nm-thick Tunnel Oxide                                               77
5.1 Introduction                                                      77
5.2 Experimental                                                     77
5.3 Results and Discussion                                             78
5.3.1   Charge Storage Effect in Capacitance-Voltage Relations            78
5.3.2   Current-Voltage Relations                                    81
5.3.3   Effect of Gate Voltage on Flat-Band Voltage                     81
5.3.4   Effect of Measurement Frequency on Flat-Band Voltage            82
5.4 Conclusions                                                      82
Chapter 6 Effect of Annealing Time on the Structural and Electrical Characteristics of Self-assembled Pt Nanocrystals in Metal-Oxide-Semiconductor Memory Structure                          94
6.1 Introduction                                                      94
6.2 Experimental                                                     95
6.3 Results and Discussion                                             96
   6.3.1   Microstructure Observation and Analysis after Annealing for Different Time                                                    96
   6.3.2   Analysis of X-ray Photoelectron Spectroscopy                    97
   6.3.3   Hysteresis in Capacitance-Voltage Relations                     98
   6.3.4   Effect of Measurement Frequency                             99
   6.3.5   Current-Voltage Relations                                   100
   6.3.6   Effect of Gate Voltage                                      101
   6.3.7   Conductance Characteristics                                 104
   6.3.8 Retention Characteristics                                      107
6.4 Conclusions                                                     107
CHAPTER 7 Summary                                             127
REFERENCE                                                     129
Appendix A Dielectric Enhancement in (001)-Textured BaTiO3/LaNiO3 Superlattices                                                       145









List of Table
Table 2.1 Performance issues of semiconductor memories                    29
Table 3.1 Sputtering conditions of the PtOx layer and gate oxide, SiO2          44
Table 3.2 Annealing condition in vauunm                                 44
Table 3.3 Sputtering conditions of Pt top electrode                          44
Table 4.1 Key parameters of the process and MOS structures in the designed experiment                                                 62
Table 4.2 Estimated densities of stored charge in the devices with different tunnel oxide 62
Table 5.1 Key parameters of the process and MOS structures in the designed experiment                                                 84
Table 5.2 Estimated densities of stored charge in the devices with different gate oxide thicknesses                                                  84
Table 6.1 Key parameters of the process and MOS structures in the designed experiment                                                109
Table 6.2 Effect of different annealing time on the composition ratio of Pt metal to Pt silicide                                                    109
Table 6.3 Estimated densities of stored charge in the devices annealed for different annealing time                                              110
List of Figure
Figure 1.1 A gap between silicon ULSI and silicon-related nanodevices           8
Figure 1.2 Three phases in the development in silicon nanodevices              8
Figure 1.3 Characteristics of a silicon dot memory. Clear hysteresis is observed only when silicon dots exist in oxide. Inset shows device structure.         9
Figure 1.4 Average electron number in silicon dots as a function of gate voltage. Inset is a MOS diode structure assumed for the calculation. Even when dot size is distributed, electron number is almost kept constant by the Coulomb blockade.                                                   9
Figure 2.1 General classification of Memories                               30
Figure 2.2 Cross-section schematic of a possible nanocrystal memory cell        30
Figure 2.3 Evolution and development of nanocrystal flash memories           31
Figure 2.4 Transistor with a distributed film of silicon nanocrystals over the tunnel oxide.                                                     31
Figure 2.5 Double sweep capacitance-voltage characteristics of MIS diode structure containing a layer of silicon nanocrystals compared to a control pure SiO2 structure                                                   32
Figure 2.6 Schematic band diagrams of different metal nanocrystals in the MOS structure shows different effective potential well depth (deff) due to the difference of different work function.                            32
Figure 2.7 Schematic cross-section of a silicon nanocrystal memory with a double layer of nanodots.                                           33
Figure 2.8 Illustration of screening effect of a single electron in a silicon nanodot with (a) nanodot charged (written), (b) nanodot uncharged (erased).        33
Figure 2.9 Schematic curve illustrating the change of drain current vs. control gate voltage for a silicon nanodot memory.                           34
Figure 2.10 Current-Voltage characteristics of a diode with embedded Sn nanodots showing a Coulomb blockade region and Coulomb staircases.       34
Figure 2.11 (a) Schematic cross section and (b) energy-band diagram of the three components of an MOS capacitor                              35
Figure 2.12 Energy-band diagrams for ideal p-type MOS capacitors under different bias conditions                                             36
Figure 2.13 Effects of Qss on the flat band voltage of the C-V relation in an ideal p-type MOS structure. (a) for negative charge (-Qss), and (b) for positive charge (+Qss).                                             37
Figure 3.1 Schematic croee-section of the Pt nanocrystal nonvolatile memory in this research                                                   45
Figure 3.2 Flow chart of the MOS device fabrication in this research            46
Figure 3.3 Schematic diagram of the dual guns RF-sputtering system            47
Figure 3.4 Flow chart of the analyses of the Pt nanocrystal memory             48
Figure 4.1 Schematic of the MOS memory device with different tunnel oxide     63
Figure 4.2 Cross-sectional TEM image of Pt nanocrystals in the device annealed at 425 ℃ for 25 min                                          63
Figure 4.3 Plane view TEM image of Pt nanocrystals in the device annealed at 425 ℃ for 25 min                                              64
Figure 4.4 Size distribution of Pt nanocrystals in the device annealed at 425 ℃ for 25 min                                                    64
Figure 4.5 HREM lattice image of isolated Pt nanocrystals in SiO2 matrix after annealing at 425 ℃ for 25 min                                 65
Figure 4.6 XPS spectra of Pt 4f electrons in reduced PtOx. Empty and solid circles indicate experimental and fitting results, respectively.               66
Figure 4.7 High-frequency C-V relations of the MOS devices with different tunnel oxide thicknesses. In the figure, s-SiO2, n-Pt and t-SiO2 denote sputtered SiO2, Pt nanocrystals and thermally-grown SiO2, respectively.        67
Figure 4.8 Schematics of the MOS device with a 2.5 (or 5.0) nm-thick tunnel oxide, applied positive or negative gate voltage (a) inversion condition, and (b) accumulation condition                                       68
Figure 4.9 Band diagrams under (a) inversion condition, and (b) accumulation condition of the nanocrystal memory device applied positive or negative gate voltage                                               69
Figure 4.10 Current-voltage (I-V) relations of all MOS devices having different tunnel oxide thicknesses                                           71
Figure 4.11 Effect of gate voltage on flat-band voltage (Vfb) and Qs of MOS devices with different tunnel oxide thicknesses (a) 2.5 nm, (b) 5.0 nm, and (c) 7.5 nm                                                      72
Figure 4.12 Effect of measurement frequency on the flat-band voltage of MOS devices with (a) 2.5 nm, (b) 5.0 nm, and (c) 7.5 nm-thick tunnel oxide layers  74
Figure 4.13 Charge retention characteristics of the Pt nanocrystals in the MOS devices with 2.5, 5.0, and 7.5 nm-thick tunnel oxide layer using a ± 8 V gate voltage stress                                              76
Figure 5.1 Schematic of the MOS memory device with different gate oxide thicknesses                                                 85
Figure 5.2 High-frequency C-V relations of MOS devices with fixed 7.5 nm-thick tunnel oxide and different gate oxide thicknesses                   86
Figure 5.3 Schematics of the MOS devices with (a) 7.5 nm (b) 2.5 (or 5.0) nm-thick tunnel oxide, applied positive gate voltage under inversion condition.  87
Figure 5.4 Modified band diagrams under (a) inversion condition, and (b) accumulation condition of the nanocrystal memory device applied positive or negative gate voltage                              88
Figure 5.5 Current-voltage (I-V) relations of all MOS devices having different gate oxide thicknesses                                            90
Figure 5.6 Effect of gate voltage on flat-band voltage (Vfb) and Qs of MOS devices with different gate oxide thicknesses (a) 12nm, (b) 24nm, and (c) 36nm 91
Figure 5.7 Effect of measurement frequency on flat-band voltage shift of C-V hysteresis in devices with different gate oxide thicknesses             93
Figure 6.1 Cross-sectional TEM images of Pt nanocrystals in SiO2 matrix for different annealing time (a) 5min, (b) 25 min and (c) 50 min                111
Figure 6.2 Plane view TEM images of Pt nanocrystals in SiO2 matrix for different annealing time (a) 5 min, (b) 25 min and (c) 50 min               113
Figure 6.3 Size distribution of Pt nanocrystals for different annealing time (a) 25 min and (b) 50 min                                             115
Figure 6.4 XPS spectra of Pt 4f electrons in reduced PtOx for different annealing time (a) 5 min, (b) 25 min and (c) 50 min. Solid and empty circles indicate experimental and fitting results, respectively.                     116
Figure 6.5 High-frequency C-V relations of MOS devices with the fixed 2.5 nm-thick tunnel oxide and fixed 24 nm-thick gate oxide for the different annealing time                                                     118
Figure 6.6 Effect of measurement frequency on flat-band voltage shift of C-V hysteresis (ΔVfb, hysteresis) in all devices with a 2.5 nm-thick tunnel oxide for different annealing time                                      119
Figure 6.7 Effect of different annealing time on current-voltage (I-V) relations of all MOS devices having a 2.5 nm tunnel oxide thickness              120
Figure 6.8 Effect of gate voltage on flat-band voltage of MOS devices with a 2.5 nm-thick tunnel oxide for different annealing time                 121
Figure 6.9 Effect of gate voltage on the Qs of MOS devices with a 2.5 nm-thick tunnel oxide for different annealing time                        122
Figure 6.10 Effect of gate voltage on the N (number of stored charge) of MOS devices with a 2.5 nm-thick tunnel oxide for different annealing time        123
Figure 6.11 Effect of positive and negative gate voltage on the N (number of stored charge) of MOS devices for different annealing time                124
Figure 6.12 Conductance characteristics of of MOS devices with the fixed 2.5 nm-thick tunnel oxide and fixed 24 nm-thick gate oxide for the different annealing time: (a) 50 min, (b) 25 min and (c) 5 min. The arrow in the figures denotes the sweeping direction of voltage.                               125
Figure 6.13 Effect of different annealing time on charge retention characteristics of Pt nanocrystals in three MOS devices with a 2.5 nm-thick tunnel oxide layer using a ± 8 V gate voltage stress                              126

                                

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