我們在此論文中提出在H.264/AVC中全文自適應二進制算術編碼的全硬體架構設計的編碼器。我們的設計中，包含了一個由二元化以及上下文模擬器組成的14組平行內文對產生器(context pair generator)，一個抓取鄰近區塊資料的三級管線架構以及一個內含前饋處理且整合三種模式的四級管線架構的算術編碼器。我們的純算術編碼器可以一個時脈處理一個位元；而且整個設計可以平均每個時脈處理0.77個位元。

We propose a full hardware implementation of Context-Based Adaptive Binary Arithmetic Encoder. Our architecture includes a 14-way context pair generator composed of binarization and context modeling, a 3-stage pipelined circuit for getting neighboring data and a 3-mode 4-stage pipelined arithmetic encoder with forwarding logic for context update. Our arithmetic encoder architecture can process one bin per cycle. The whole encoder is able to process 0.77 bins per cycle on the average.

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