隨著晶片製程的發展，單一晶片上可容納的處理元件也日益增多，根據Moore's law，電路中的的電晶體是以每兩年倍增的速率在增加，也表示往後單一系統晶片上的處理單元只會越來越多，現有的SoC技術也面臨著性能、功耗、可擴展性和延遲等等的挑戰。晶片設計重點也漸漸由增加每個處理元件的效能，改變成如何讓每個處理元件能更有效率的合作解決問題，在這種情況下單晶片網路(Network on-Chip)的設計課題也應運而生。
在單晶片網路的設計理念中，有許多不同的拓樸架構，其中包含了2DMesh、2DTorus、Tree、Ring等等，環型拓樸結構一方面由於其結構較為簡單容易實現，另一方面節點之間又具有固定的距離所以傳輸的延遲可以預先確定，較為適合目前MPSoC和CMP技術中的處理器數目，因此成為了最早商業化的NoC拓樸結構之一。而在本篇論文中，我將使用Verilog 硬體描述語言(HDL)來實作一種多環環型拓樸結構(Multi-Ring topology)，在文章中我們將深入探討內部的結構組成並且針對幾種不同的交通模組進行效能的分析，同時在多環環型拓樸結構的基礎下，我將增加其同方向的環可以進行交叉傳輸的功能，稱為交叉多環環型拓樸結構(Cross Multi-Ring topology)，並使用幾種不同的交通模組針對以上兩種拓樸結構進行效能優劣的比較和評估，以及在FPGA上的合成結果。而在最後的模擬結果，我們將發現效能和交叉傳輸的使用率之間正相關的關係。

[1] R. Schaller, “Moore’s law: past, present and future,” Spectrum, IEEE, vol. 34, no. 6,
pp. 52–59, 1997.
[2] A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, M. Millberg, and D. Lindqvist,
“Network on chip: An architecture for billion transistor era,” in Proceeding of the IEEE
NorChip Conference, vol. 31, 2000.
[3] S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and
A. Hemani, “A network on chip architecture and design methodology,” in VLSI, 2002.
Proceedings. IEEE Computer Society Annual Symposium on. IEEE, 2002, pp. 105–
112.
[4] W. Dally and B. Towles, Principles and practices of interconnection networks. Morgan
Kaufmann, 2003.
[5] T. Chen, R. Raghavan, J. Dale, and E. Iwata, “Cell broadband engine architecture and
its first implementation—a performance view,” IBM Journal of Research and Development,
vol. 51, no. 5, pp. 559–572, 2007.
[6] M. Kistler, M. Perrone, and F. Petrini, “Cell multiprocessor communication network:
Built for speed,” Micro, IEEE, vol. 26, no. 3, pp. 10–23, 2006.
[7] J. Duato, S. Yalamanchili, and L. Ni, Interconnection networks. Morgan Kaufmann,
2002.
[8] W. Dally and C. Seitz, “The torus routing chip,” Distributed computing, vol. 1, no. 4,
pp. 187–196, 1986.
[9] M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, and A. Scandurra, “Spidergon:
a novel on-chip communication network,” in System-on-Chip, 2004. Proceedings. 2004
International Symposium on. IEEE, 2004, p. 15.
[10] T. Ainsworth and T. Pinkston, “Characterizing the cell eib on-chip network,” Micro,
IEEE, vol. 27, no. 5, pp. 6–14, 2007.
[11] G. De Micheli and L. Benini, Networks on chips: technology and tools. Morgan Kaufmann,
2006.
[12] I. DeveloperWorks, “Meet the experts: David krolak on the cell broadband engine eib
bus,” 2005.
[13] O. Initiative, “Systemc 2.0. 1 language reference manual,” Revision, vol. 1, no. 1177,
pp. 95 118–3799, 2003.
[14] J. Kahle, M. Day, H. Hofstee, C. Johns, T. Maeurer, and D. Shippy, “Introduction to
the cell multiprocessor,” IBM journal of Research and Development, vol. 49, no. 4.5,
pp. 589–604, 2005.
[15] D. Tala, “Verilog tutorial,” www. asic-world. com, 2003.
47