近年來，行動裝置的數量越來越多，人們除了對行動裝置的功能很重視外，對傳輸的品質更是格外的要求，因此，空時排列調變多輸入多輸出（STPM-MIMO）因而被提出，它為一種新的多天線多輸出技術且擁有良好的傳輸穩定度。

基於空時排列調變多輸入多輸出技術，本篇論文提出三種偵測器的演算法，包含球面偵測器（Sphere Detector）、排序球面偵測器（Ordered Sphere Detector）以及多候選選擇匹配最高比結合偵測器（Multiple Candidate Selection Matched-MRC Detector）。球面偵測器以及排序球面偵測器為最佳偵測器（Optimal Detector），它們的位元錯誤率與最大似然偵測器（Maximum-Likelihood Detector）相同。球面偵測器的運算複雜度在高訊雜比時，大概只有最大似然偵測器的15.6%。排序球面偵測器可以改善球面偵測器搜尋的效率，因此在高訊雜比時，排序球面偵測器的運算複雜度約只有球面偵測器複雜度的33%。雖然球面偵測器與排序球面偵測器擁有最大似然偵測器的位元錯誤率表現，但它們並不適合用於硬體實現。多候選選擇匹配最高比結合偵測器為次最佳偵測器，但其非常適合實作於硬體，它的運算複雜度在訊雜比為30dB以及0dB時僅只有排序球面偵測器複雜度的10%以及5%，但只有不到0.15dB的表現損失。

本篇論文最後用現場可程式化閘陣列（Field－Programmable Gate Array）(xc7vx690t-3ffg1157)實作以及驗證多候選選擇匹配最高比結合偵測器，並且提出兩種版本的硬體，第一個版本擁有較高的吞吐量(539Mbps)但相對用了較多FPGA的資源；另一個版本的吞吐量(8.8Mbps)較低但使用非常少FPGA的資源。此外，硬體的時序以及FPGA資源使用率的分析也將呈現於本論文中。

In the past few years, the number of mobile devices are more and more. Not only to the functions of the mobile devices, people attach great importance to the transmission quality as well. A new MIMO technology called Space-Time Permutation Modulation MIMO(STPM-MIMO) has additional consideration about transmission reliability.

Based on the STPM-MIMO technology, this thesis proposes three detector algorithms, which are Sphere detector(SD), Ordered Sphere detector(OSD) and Multiple Candidate Selection Matched-MRC detector(MCSMMD) algorithms. SD and OSD algorithms are optimal detector algorithms, and their BER performances are the same as the benchmark, Maximum-Likelihood(ML) detector algorithm. The computing complexity of SD algorithm is about 15.6 percent of ML detector algorithm at high SNR. OSD algorithm can improve the efficiency of SD algorithm. The computing complexity of OSD algorithm is approximately 33 percent of SD algorithm at high SNR. Although SD and OSD algorithms have the ML performance, they are not suitable for hardware implementation. MCSMMD algorithm is sub-optimal detector algorithm; however, it is a easier and flexible hardware implementation detector algorithm. The computing complexity of MCSMMD algorithm is approximately 10 and 5 percent of OSD algorithm with very little performance loss at SNR 30 and 0 dB, respectively.

In this thesis, two versions of hardware architecture of MCSMMD algorithm are proposed, implemented and verified by FPGA(xc7vx690t-3ffg1157). One version has higher throughput(539Mbps) but higher utilization; the other version has lower throughput(8.8Mbps) but lower utilization. The analysis of hardware timing and hardware area are also presented in the end.

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