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研究生: 鄭照霖
Cheng, Chao-Lin
論文名稱: 利用微懸臂樑測試鍵萃取CMOS製程之薄膜機械性質
Determining the Thin Film Mechanical Properties for CMOS Processes Using Micro Test Cantilevers
指導教授: 方維倫
Fang, Weileun
口試委員: 鄭裕庭
李昇憲
林宗賢
盧向成
羅炯成
學位類別: 博士
Doctor
系所名稱: 工學院 - 動力機械工程學系
Department of Power Mechanical Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 121
中文關鍵詞: CMOS MEMS楊氏模數熱膨脹係數殘餘應力懸臂樑
外文關鍵詞: CMOS MEMS, Elastic modulus, CTE, Residual stress, Cantilever beam
相關次數: 點閱:3下載:0
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  • 標準製程發展微機電元件有逐步增加趨勢,而CMOS製程製作MEMS結構已有許多文獻提出,然而在機械結構設計卻無相關機械性質等參數。因此,本研究期望建立一套量測方法與參數資料庫,提供往後設計者更符合實際平台的薄膜機械性質。本研究採用現有文獻方法分析標準CMOS製程平台之金屬與介電層之機械性質,包含楊氏模數、熱膨脹係數及殘餘應力等。設計與製作具有不同金屬與介電層堆疊組成之懸臂樑測試鍵,因此標準CMOS製程之薄膜楊氏模數、熱膨脹係數及殘餘應力,透過量測微懸臂樑之結構共振頻率、出平面方向之熱變形,以及初始變形量,分別求解相關機械特性。為了驗證所採用的求解CMOS薄膜機械性質方法,本研究針對台灣積體電路製造股份有限公司(TSMC) 0.35um 2P4M CMOS標準製程進行各層薄膜性質萃取。在CMOS晶片上設計與製作八組不同堆疊之懸臂樑測試鍵,以及利用SOI晶圓製作之輔助矽懸臂樑作為測試鍵。因此,CMOS製程中金屬及介電層的等效楊氏模數、熱膨脹係數,分別量測懸臂樑之動態響應及靜態熱變形求解。另外,CMOS薄膜殘餘應力透過量測微懸臂樑初始靜態變形,搭配邊界旋轉法與Timoshenoko雙層理論進行計算。此外,設計與前述不同堆疊的懸臂量測試鍵,驗證萃取薄膜機械性質之實用性。


    Standard process to develop MEMS device has gradually increased, especially exploiting CMOS process to implement MEMS device had been proposed. However, there is no complete mechanical properties database to provide designer in structural design. Therefore, in this study, expecting to establish an extraction methodology and mechanical properties database. This study employs an existing approach to determine the elastic modules, coefficient of thermal expansion (CTE), and residual stress of metal and dielectric films for standard CMOS processes. The test cantilevers with different stacking of metal and dielectric layers for standard CMOS process have been designed and implemented. Thus, the elastic modules, CTE, and residual stress of standard CMOS films can be respectively determined after the frequency responses, out-of-plane thermal deformations, and initial deformation of test cantilevers are measured. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) 0.35m 2P4M CMOS process were characterized. Eight test cantilevers with different stacking of CMOS layers and the auxiliary Si cantilever on SOI wafer are fabricated. The equivalent elastic modulus and CTE of CMOS thin films includes the metal and dielectric layers are respectively determined by the resonant frequency and static thermal deformation of test cantilevers. The residual stress of CMOS films are respectively determined by boundary rotation method and Timoshenko bi-layer theory. Moreover, cantilevers with different layer-stacking other than those of the test beams have been employed to verify the measured properties.

    中文摘要 i Abstract ii 目 錄 iii 圖目錄 vi 表目錄 x 第一章 緒論 1 1-1 前言 1 1-2 文獻回顧 2 1-2-1 薄膜楊氏模數萃取 3 1-2-2 薄膜熱膨脹係數萃取 4 1-2-3 薄膜殘餘應力萃取 5 1-3 研究動機 9 1-4 研究目標與架構 11 第二章 多層薄膜堆疊測試結構設計 21 2-1 懸臂樑測試鍵堆疊組合 21 2-2 懸臂樑測試鍵之後製程 22 2-3 金屬蝕刻後製程之誤差源 25 第三章 薄膜楊氏模數 36 3-1 理論分析 36 3-2 後製程製作 37 3-3 求解流程 38 3-4 量測結果 39 3-5 分析與討論 41 第四章 薄膜熱膨脹係數 50 4-1 理論分析 50 4-2 後製程製作 51 4-3 求解流程 52 4-4 量測結果 54 4-5 分析與討論 55 第五章 薄膜殘餘應力 64 5-1 理論分析 64 5-1-1 邊界旋轉理論 65 5-1-2 雙層薄膜理論 66 5-2 後製程製作 68 5-3 求解流程 69 5-4 量測結果 71 5-5 分析與討論 72 第六章 論文貢獻與未來工作 82 6-1 建立CMOS MEMS薄膜機械特性資料庫 82 6-2 建立薄膜機械特性萃取方法 82 6-3 萃取參數於壓力感測器應用 83 參考文獻 87 附錄A 具效能提升之壓力感測器 98 A-1 壓力感測器設計與分析 98 A-2 製程流程與結果 101 A-3 量測結果與討論 103 附錄B UMC標準CMOS MEMS製程平台 115 B-1 UMC 0.18um 1P6M CMOS MEMS平台簡介 115 B-2 UMC 0.18um 1P6M CMOS MEMS製程流程 115 B-3 製程與量測結果 116 研究著作 121

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