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研究生： 林志忠
Chih-Chung Lin
論文名稱： 進階微控制器晶片內建匯流排架構(AMBA)之實現
Implementation of On-Chip-Bus - AMBA
指導教授： 張世杰
Shih-Chieh Chang
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2002
畢業學年度： 90
語文別： 中文
論文頁數： 66
中文關鍵詞： 進階微控制晶片內建匯流排架構 、內建晶片匯流排
外文關鍵詞： AMBA, On-Chip-Bus
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    • 我們將目前內建單晶片匯流排的標準規格之一,AMBA以硬體描述語言的方式將它設計實現出來。內建單晶片匯流排的架構是許多的子系統透過共用一組接線使得彼此之間能夠互相傳輸資料。在系統單晶片的設計領域中,匯流排架構必須提供一種整合的方式使系統能達到有效、高速和低功率的整合。AMBA的規格是由ARM Limited所提出並推動的單晶片匯流排架構。AMBA在系統單晶片整合中提供了一種很好的解決方式。AMBA是一種On-Chip-Bus的規格，裡面定義了三種Bus – AHB、ASB、APB。AHB和ASB皆是系統匯流排，而APB是周邊匯流排。AHB和ASB能提供高效率的,多功能的傳輸模式,適用於高速的裝置。而APB能提供比較簡單的傳輸介面讓一些低功率的周邊裝置互相連接。而AHB或ASB如要和APB互相溝通則須透過橋接器(Bridge)。
    在本篇論文中,我們將AMBA規格中各個的成員一一實現出來,包括主從介面、仲裁模組、位址解碼器和橋接器。除此之外,我們將一些矽智產(IP)模組,包括ARM行為模組、記憶體行為模組、直接存取記憶體(DMA)模組和一個加解密的模組進行wrapper的設計,使得可以接連在AMBA上面。為了驗證我們發展AMBA架構的正確性,我們將這些矽智產模組整成成為一個以AMBA為基本架構的系統。我們在這個整合好的系統上以ARM模組當作系統控制者,控制整個系統來進行加解密的動作。

    We implement one of on-chip-bus standard – AMBA (Advanced Microcontroller Bus Architecture). On-chip-bus architecture is a shared common link, which use one set of wires to connect multiple subsystems. In SOC design, bus architecture must provide efficiently, high performance and low power integration. AMBA specification was released from ARM Limited from 1995. AMBA provides good integration solution in SOC design. In this thesis, we design each component in AMBA, including master, slave, arbiter, decoder and bridge. Besides, we design ARM behavior wrapper as a system controller, memory controller wrapper, DMA controller wrapper and an AES IP wrappers by reusing AMBA components. We build a system based on AMBA architecture for verifying the AMBA transfer protocol. This system integrates the AES IP and controls the IP to do the encryption/decryption operations. The designs of AMBA components are described in Verilog hardware description language and are synthesizable.

    Contents ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES V CHAPTER 1 1 INTRODUCTION 1 CHAPTER 2 4 SPECIFICATION OF AMBA 4 2.1 INTRODUCTION OF AMBA 4 2.2 AMBA AHB 7 2.2.1 AHB Basic transfer 10 2.2.2 AHB Transfer Type 11 2.2.3 Burst transfer 13 2.2.4 Slave transfer response 14 2.2.5 Two-cycle response — ERROR, RETRY and SPLIT 16 2.2.6 Arbitration 18 2.2.7 Split transfer 20 2.3 AMBA APB 20 2.3.1 The transfer protocol of APB 20 CHAPTER 3 24 AMBA COMPONENTS DESIGN 24 3.1 AHB ARBITER 24 3.1.1 AHB Arbiter I/O interface 24 3.1.2 AHB Arbiter Architecture 25 3.1.3 Priority Block 26 3.1.4 Arbiter controller 27 3.2 AHB DECODER 29 3.3 AHB MASTER 30 3.3.1 AHB Master I/O interface and architecture 30 3.4 AHB SLAVE 32 4.1.1 AHB Slave I/O interface and architecture 32 3.5 APB BRIDGE 34 3.5.1 APB Bridge I/O interface and architecture 34 3.6 APB SLAVE 36 CHAPTER 4 37 SYSTEM INTEGRATION AND VERIFICATION 37 4.1 AMBA WRAPPER DESIGN FOR IPS 37 4.1.2 Memory controller wrapper design 37 4.1.3 DMA controller wrapper design 38 4.1.4 AES wrapper design 41 4.2 SYSTEM INTEGRATION AND VERIFICATION 45 4.2.1 Setup the address space of each slave 47 4.2.2 Setup the default master 47 4.2.3 Simulation flow 48 CHAPTER 5 50 EXPERIMENT RESULTS 50 5.1 SYNTHESIS RESULTS OF AMBA COMPONENTS 50 5.2 APPLICATION SIMULATION WAVEFORMS 51 5.2.1 THE ARM CONTROLLER FETCH INSTRUCTIONS 51 5.2.2 THE AES WRAPPER SIMULATION WAVEFORMS 52 5.2.3 THE DMA WRAPPER SIMULATION WAVEFORM 53 CHAPTER 6 54 CONCLUSIONS 54 APPENDIX A 55 SIGNAL DESCRIPTIONS 55 A.1 SIGNAL DESCRIPTION OF AMBA INTERFACE 55 A.2 SIGNAL DESCRIPTION OF AHB MASTER WRAPPER INTERFACE 57 A.3 SIGNAL DESCRIPTION OF AHB SLAVE INTERFACE 58 A.4 SIGNAL DESCRIPTION OF APB SLAVE INTERFACE 58

    [1] AMBA specification, refer to ARM Limited web page: http://www.arm.com
    [2] J. Hennessey and D. Patterson, Computer Organization & Design, 2nd ed., Morgan Kaufmann, San Mateo, Calif., 1998.
    [3] An AES Rijndael Cipher Design, refer to AES web page: http://csrc.nist.gov/encryption/aes/rijndael.
    [4] Virtual Components Interface Standard, refer to VSIA web page: http://www.vsi.org
    [5] David Flynn, “AMBA: Enabling Reusable On-Chip Designs”, IEEE Micro, 1997, pp. 20-27.
    [6] Roman L. Lysecky, Frank Vahid, Tony D. Givargis, “Techniques for Reducing Read Latency of Core Bus Wrappers”, Design, Automation and Test In Europe, 2000
    [7] Bob Zeidman, Verilog Designer’s Library, Prentice Hall PTR, 1999.
    [8] ARM 7TDMI Data Sheet, refer to ARM web page: http://www.arm.com
    [9] Dave Jaggar, Advanced RISC Machines Architecture Reference Manual, Prentice Hall, 1996.
    [10] David R. Smith, Paul D. Franzon, Verilog Styles for Synthesis of Digital Systems, Prentice Hall, 2000.
    [11] Steve Furber, ARM System Architecture, ADDISON-WESLEY, 1996
    [12] Roman L. Lysecky, Frank Vahid, Tony D. Givargis, “Experiments with the Peripheral Virtual Component Interface”, IEEE , 2000, pp.221-224.
    [13] ARM PrimeCell Single Master DMA Controller Techniques Reference Manual, refer to ARM web page: http://www.arm.com.

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