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研究生： 張積福
Chang, Chi-Fu
論文名稱： 單晶片網路系統探索平台之設計與實做
Design and Implementation of an NOC-centric System Exploration Platform
指導教授： 許雅三
Hsu, Yar-Sun
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2009
畢業學年度： 97
語文別： 中文
論文頁數： 227
中文關鍵詞： 單晶片網路 、單晶片網路模擬 、網路模型化
外文關鍵詞： Network-on-chip, NoC, NoC simulator, NoC modeling
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    • 因為製程進步，單晶片系統(System on Chip)能置入越來越多的計算核心、加速器、智財單元(IP units)等，效能瓶頸漸漸發生在系統的通訊結構上。為了解決此問題，單晶片網路(network on chip)是一個熱門的解決方案。為了從系統角度模擬單晶片網路的設計，有許多單晶片網路模擬器被建立貣來。這篇論文的貢獻，在於提供一個新的單晶片網路模擬器 – Nocsep，意即「單晶片網路為核心的系統探索平台」。它提供三方面的成果：(1)完整的系統框架與多樣的系統元件。從軟體層到硬體層的交通樣式(traffic pattern)藉此被建立貣來。(2)不同抽象層級的元件模型設計。藉此我們能大量重複使用程式碼並加速建構一個新的單晶片網路設計。(3)整合的效能評估環境。這個環境100%相容於SystemC的任意模型設計，所以使用非常有彈性。藉由Nocsep的模擬平台，一個系統被分割成許多層級(layer)、每個層級被化約成許多元件(component)、每個元件都使用多抽象階層(multi-abstraction level)、多遲滯參數(latency parameter)的週期逼近準確模型來描述。因此Nocsep所能支援的NoC模擬的探索空間非常大。這篇論文將說明Nocsep的一切設計與實做細節，並在結尾時展示一些模擬成果。

    As the traffic load increases, System-on-Chip faces the performance bottleneck in the communication architecture. Network-on-chip is a popular solution. It uses many inventions from wide-area networks and on-board multi-processor communication structures, and shrinks their scale to the chip level. There are many system-level simulators for Network-on-chip design. This paper presents our work, Nocsep, standing for ―Network-On-Chip-centric System Exploration Platform‖. It provides (a) an on-chip system framework with which we can build up the entire on-chip traffic across network layers, (b) the multi-abstraction-level components for each network layer to reduce the coding effort for a new NoC design, and (c) a system performance estimation environment highly compatible to any traditional SystemC designs with some improved features. In Nocsep, the design space of an NoC-centric system is clearly divided. One system is divided into many layers. One layer is divided into many components. One component is divided into many abstraction levels and one abstraction level is divided into many stages. Each stage is estimated in the latency model which has many latency parameters. Therefore we can claim that Nocsep design space is much larger than other existent NoC simulators. Most importantly, all the Nocsep models are implemented in practice thoroughly in SystemC codes and some demonstrations are discussed at the end of this paper.

    CHAPTER 1 INTRODUCTION 1.1 WHAT IS NETWORK-ON-CHIP-CENTRIC SYSTEM EXPLORATION PLATFORM (NOCSEP)? 1.2 RESEARCH MOTIVATION 1.3 THE CONSTRUCTION OF NOCSEP CHAPTER 2 RELATED WORKS 2.1 NOC RESEARCH BACKGOUND 2.2 NOC SIMULATION FRAMEWORK 2.3 CURRENT NOC SIMULATION FRAMEWORK RESEARCH ＆ NOCSEP CONTRIBUTIONS CHAPTER 3 NOCSEP DESIGN CONCEPT 3.1 NOCSEP PHILOSOPHY 3.2 NOCSEP SYSTEM FRAMEWORK OVERVIEW 3.2.1 Nocsep System Layering 3.2.2 Nocsep System Latency Model 3.2.3 Nocsep System Layer Interface & Interface Implementation 3.2.4 Design Exploration Approach 3.3 NOCSEP SERVICE HANDLER MODEL DESIGN 3.4 NOCSEP SERVICE MODEL DESIGN 3.5 COMPLETE VIEW OF ALL NOCSEP MODELS 3.6 NOCSEP MULTIPLE ABSTRACTION LEVEL MODELING METHOD 3.6.1 Systematic Implementation 3.6.2 Use The Smallest Effort for Model Modification 3.7 NOCSEP SIMULATION ENVIORNMENT 3.7.1 ―TBlock― Object 3.7.2 File-Discribed System Composing 3.7.3 Nocsep Simulation Flow CHAPTER 4 NOCSEP DEFAULT DESIGN LIBRARY 4.1 OVERVIEW OF NOCSEP DEFAULT DESIGN LIBRARY 4.2 OVERVIEW OF DEFAULT HARDWARE RESOURCE 4.2.1 Buffer—Default Buffer Interface, Template, Function Block, and Component Designs 4.2.2 Physical Channel —Default PC Interface, Template, Function Block, and Component Designs 4.2.3 Implicit Buffer (local Store) Issues 4.3 OVERVIEW OF DEFAULT OCCA COMPONENT DESIGNS 4.4 DEFAULT DATA-LINK-LAYER CHANNEL—DEFAULT DC INTERFACE, TEMPLATE, FUNCTION BLOCK, AND COMPONENT DESIGNS 4.4.1 DC Default Function Block Implementations 4.4.2 DC Default Template Design 4.5 DEFAULT DC LINKER COMPONENT (ROUTING AND FLOW CONTROL UNIT) AND NETWORK INFORMATION DESK DESIGN 4.6 NOCSEP DEFAULT OCCA DESIGNS 4.6.1 Single Switch & General Switch 4.6.2 Sinple BUS 4.6.3 Crossbar 4.6.4 Mesh 4.6.5 Double Ring 4.6.6 Binary Tree Network 4.6.7 2x2x2 Multi-stage Network 4.7 DEFAULT ADAPTOR COMPONENT DESIGN 4.8 DEFAULT APPLICATION PLATFORM – PACMDL & NODE MODEL 4.8.1 PACMDL & Thread Component 4.8.2 Default Node Component 4.8.3 Application Throughput Issues CHAPTER 5 DEMONSTRATIONS OF NOCSEP 5.1 DEFAULT PARAMETER SETUP AMONG ALL CASES 5.1.1 Default Simulation Platform 5.1.2 Performance Estimation Metrics 5.2 SIMULATION DATA AND GRAPHS 5.2.1 Crossbar Switch Behaviors 5.2.2 Mesh, Double Ring, Binary Network, Multi-stage Network 5.2.3 Task Graph Application Case Study 5.2.4 Common Parameters of All Case Studies CHAPTER 6 CONCLUSION AND FUTURE WORKS BIBLIOGRAPHY APPENDIX I – PACMDL COMMAND FORMAT APPENDIX II –THE CASE STUDY OF MATRIX MULTIPLYING BETWEEN COWARE PLATFORM AND NOCSEP PLATFORM

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