中文摘要
本文主要研究建構在半絕緣基板之4H-SiC橫向高電壓 RESURF元件之關鍵設計參數,並經由模擬及實際元件製作來測試驗證。表面電荷, 場平板, 電荷平衡狀況對崩潰電壓之影響等皆列入模擬.從模擬結果來看，場平板可降低電場集中現象而表面電荷在電荷平衡上扮演關鍵地位.相較於單漂移區之設計,雙漂移區RESURF架構可產生額外之電場峰值, 因而可將具100微米漂移區之元件崩潰電壓從 5880 V提升至8000 V.
我們製作了建構於半絕緣基板上之橫向高電壓元件 PN二極體, 接面場效電晶體, 金氧半場效電晶體,絕緣閘極雙極電晶體以驗證我們所提出結構之優點.製程中我們加入N2O退火,載子生命週期改善等不同製程以強化順向導通特性. 為了解高壓與低壓元件整合於單一晶片之可行性, 我們製作了一顆互補金氧半場效電晶體反向器並測試其性能.
本研究主要達成之成果為:
1. 製作出100微米雙漂移區橫向接面場效電晶體具有導通電阻454 mΩ-cm2及崩潰電壓4200 V,達到 FOM值 38.8 MW/cm2 .
2. 製作出40微米單漂移區橫向金氧半場效電晶體具有導通電阻115 mΩ-cm2及崩潰電壓2460 V,達到 FOM值 52 MW/cm2 .
3. 首次製作出建構於半絕緣基板上之4H-SiC高電壓橫向絕緣閘極雙極電晶體. 80微米單漂移區橫向絕緣閘極雙極電晶體達到導通電阻425 mΩ-cm2及崩潰電壓2670 V之性能.利用載子生命週期改善製程達成PN二極體與絕緣閘極雙極電晶體之初步順向特性改善. PN二極體順向導通電壓降低5.5%, 絕緣閘極雙極電晶體共基極電流增益達到0.3.另外本文也對溫度,注入效率與載子生命週期對絕緣閘極雙極電晶體性能之影響做了研究分析及歸納

Abstract
Critical design issues for 4H-SiC lateral devices on a semi-insulating substrate with a RESURF structure have been investigated and verified through simulation and experiment. The dependence of breakdown voltage on surface charges, field plates, and charge imbalance conditions was simulated. From simulation results, it is evident that the field plates help reducing the electric field crowding and the surface charges play a critical role in the charge imbalance analysis. Compared to single zone, a two-zone RESURF structure is able to create an additional peak in the electric field profile, thus increasing the Breakdown Voltage ( BV) from 5880 to 8000 V for a device with a drift region length of 100 μm.
The lateral High-Voltage devices on semi-insulating substrate including PN diode, JFET, MOSFET, and IGBT were fabricated and characterized to verify the advantages of the proposed structure. Various process improvement, such as N2O annealing, lifetime enhancing, was also done to better the forward characteristic. To check the feasibility of integrating High-voltage with low-voltage devices on a chip, a CMOS inverter was fabricated and tested. The main achievements of this study are
(1) The two-zone lateral JFET with Ld of 100 μm exhibits a specific on-resistance of 454 mΩ-cm2 and a BV of 4200 V, having a figure of merit of 38.8 MW/cm2.
(2) The single-zone lateral MOSFET with Ld of 40 μm shows a Ron,sp of 115 mΩ-cm2 and a BV of 2460 V. The FOM is as high as 52 MW/ cm2.
(3) A 4H-SiC lateral High-Voltage IGBT on semi-insulating substrate is demonstrated for the first time. An Ron,sp of 425 mΩ-cm2 and a BV of 2670 V was obtained for sin-gle-zone lateral IGBT with Ld of 80 μm. PN diodes and IGBTs with carrier lifetime enhancement exhibit a preliminary improvement in forward characteristics. For PN, a 5.5% voltage drop reduction was reached. For IGBT, a common base current gain of 0.3 was obtained. The influence of temperature, injection efficiency and lifetime on IGBT performance was investigated and summarized.

References

[1] C.-M. Zetterling et al.,“Process Technology for
Silicon Carbide Devices,” in EMIS processing series,
IEE, 2002.
[2] V. Kumar, A. Kuliev, R. Schwindt, M. Muir, G. Simin, J.
Yang, M. A. Khan, and I. Adeshida, “High performance
0.25 lm gate-length AlGaN/GaN HEMTs on sapphire with
power density of over 4.5 W/mm at 20 GHz,” Solid-State
Electron, vol. 47, 1577-1580, 2003.
[3] Y. F. Wu, A. Saxler, M. Moore, R. P. Smith, S.
Sheppard, P. M. Chavarkar, T. Wisleder, U. K. Mishra,
and P. Parikh, “30-W/mm GaN HEMTs by field plate
optimization,” IEEE Electron Device Letters, vol. 25,
no. 3, pp. 117–119, Mar. 2004.
[4] M. Higashiwaki, T. Mimura, and T. Matsui, “30-nm-Gate
AlGaN/GaN Heterostructure Field-Effect Transistors with
a Current-Gain Cutoff Frequency of 181 GHz,” Japanese
Journal of Applied Physics, vol. 45, L1111-L1113, 2006.
[5] G. R. Fisher and P. Barnes, “Toward a Unified View of
Polytypism in Silicon Carbide,” Phil. Mag. B, vol. 61,
no. 2, pp. 217–236, Feb.1990.
[6] A. R. Powell and L. B. Rowland, “SiC Materials-
Progress, Status, and Potential Roadblocks,”
Proceedings of the IEEE, vol. 90, no. 6, June 2002
[7] M. Kanaya, J. Takhashi, Y. Fujiwara, and A.
Moritani, “Controlled Sublimation Growth of Single
Crystalline 4H-SiC and 6H-SiC and Identification of
Polytypes by X-ray Diffraction,” Applied Physics
Letter, vol. 58, pp. 56, Jan. 1991.
[8] G. Augustine, et al., “Physical Vapor Transport Growth
and Properties of SiC Monocrystals of 4H poly-
type,Physics Status Solidi (b), vol. 202, no. 1, pp.
137, July 1997.
[9] R. A. Stein and P. Lanig, “Control of Polytype
Formation by Surface Energy Ef-fects during the Growth
of SiC Monocrystals by the Sublimation Method,” Jour-
nal of Crystal Growth, vol. 131, no. 1, pp. 71, July
1993.
[10] Straubinger, et al., “Stability Criteria for 4H–SiC
Bulk Growth,” Material Science Forum, vol. 353–356,
pp. 55, 2001.
[11] CREE Research Inc., N.C., U.S.A.
[12] S. K. Lee., “Processing and Characterization of
Silicon Carbide (6H- and 4H-SiC) Contacts for High
Power and High Temperature Device Applications,” Ph.D
Dissertation, Department of Electronics, KTH, Royal
Institute of Technology, Stockholm, Sweden , 2002.
[13] T. Kimoto, H. Nishino, W. S. Yoo, and H.
Matsunami, “Growth Mechanism of 6H-SiC in Step
Controlled Epitaxy,” Journal Applied Physics, vol.
73, pp. 726, 1993.
[14] M. Lades, W. Kaindl, N. Kaminski, E. Niemann, and G.
Wachutka, “Dynamics of Incomplete Ionized Dopants and
Their Impact on 4H/6H–SiC Devices,” IEEE
Transactions on Electron Devices, vol. 46, no. 3, Mar.
1999
[15] T. Hiyoshi and T. Kimoto, “ Reduction of Deep Levels
and Improvement of Car-rier Lifetime in n-Type 4H-SiC
by Thermal Oxidation,” Applied Physics Express, vol.
2, no. 041101, 2009
[16] A. Galeckas, J. Linnros, V. Grivickas, U. Lindefelf,
and C. Hallin, ” Auger Rcombination in 4H-SiC:
Unusual Temperature Behavior,” Applied Physics
Letters vol. 71, pp. 3269, 1997.
[17] J. Wang and B. W. Williams, “ Evolution of High-
Voltage 4H–SiC Switching Devices,” IEEE Transactions
on Electron devices, vol. 46, no. 3, Mar. 1999
[18] J. H. Yim, H. K. Song, J. H. Moon, H. S. Seo, J. H.
Lee, H. J. Na, J. B. Lee, and H. J. Kim, “4H-SiC
planar MESFETs on High-Purity Semi-Insulating Sub-
strates,” Material Science Forum, vol. 556-557, pp.
763–766, 2007.
[19] T. Kimotoa, S. Nakazawa, K. Hashimoto, and H.
Matsunami, “Reduction of Doping and Trap
Concentrations in 4H-SiC Epitaxial Layers Grown by
79, no. 17, pp. 2761–2763, Oct. 2001.
[20] A. Pérez-Tomás, P. Brosselard, P. Godignon, and J.
Millán, “Field-effect Mobil-ity Temperature Modeling
of 4H-SiC Metal-Oxide-Semiconductor Transistors,”
Journal of Applied Physics, vol.100, no.114508, 2006
[21] D. K. Schroder, “Semiconductor Material and Device
Characterization,” John Wiley & Sons, Inc., 2006.
[22] J. Baliga, “Silicon Carbide Power Devices,” World
Scientific Company, 2005
[23] S. Tanimoto et al., “Ohmic Contact Structure and
Fabrication Process Applicable to Practical SiC
Devices,” Material Science Forum, vol. 389-393, pp
879-884, 2002.
[24] J. H. Park and P. H. Hollowaya, “Interfacial
Reactions in Nickel/Titanium Ohmic Contacts to N-type
Silicon Carbide,” Journal of Vacuum Science
Technology B vol.23, no.6, Nov/Dec 2005.
[25] B. J. Johnsona and M. A. Capano, “Mechanism of Ohmic
behavior of Al/Ti con-tacts to p-type 4H-SiC after
annealing,” Journal of Applied Physics, vol. 95, no.
10, May 2004.
[26] M. E. Zvanut, V. V. Konovalov, H. Wang, W. C. Mitchel,
W. D. Mitchell et al., “Defect levels and Types of
Point Defects in High-purity and Vanadium-doped Semi-
insulating 4H–SiC,” Journal of Applied Physics, vol.
96, no. 10, Nov. 2004.
[27] W. C. Mitchela and W. D. Mitchell, “Compensation
Mechanism in High Purity Semi-insulating 4H-SiC,”
Journal of Applied Physics, vol. 101, no. 053716,
2007.
[28] 4H-SiC product list, Cree Inc. 2011
[29] P. G. Muzykov, R. M. Krishna, and K. C.
Mandal, “Temperature Dependence of Current Conduction
in Semi-insulating 4H-SiC Epitaxial Layer,” Applied
Phys-ics Letters, vol.100, no. 032101, 2012.
[30] J. W. Palmour, J. A. Edmond, H. S. Kong, and C. H.
Carter, “6H-Silicon Carbide Power Devices for
Aerospace Applications,” in Proceedings of 28th
Intersociety Energy Conversion Energy Conference,
1993, pp. 1249–1254.
[31] J. N. Shenoy, J. A. Cooper, Jr., and M. R.
Melloch, “High-voltage Double Im-planted Power
MOSFETs in 6H-SiC,” IEEE Electron Device Letters,
vol. 18, no. 3, pp. 93–95, Mar. 1997.
[32] S. H. Ryu, A. Agarwal, and J. Richmond et al., “Large-
area (3.3 mm × 3.3 mm) Power MOSFETs in 4H-SiC,”
Material Science Forum, vol. 389–393, pp. 1195–1198,
2002.
[33] Y. Li, J. A. Cooper, Jr., and M. A. Capano, “High-
voltage (3 kV) UMOSFETS in 4H-SiC,” IEEE Transactions
on Electron Devices, vol. 49, no. 6, pp. 972–975,
Jun. 2002.
[34] I. A. Khan, J. A. Cooper, Jr., M. A. Capano, T. Isaacs-
Smith, and J. R. Williams, “High-voltage UMOSFETs in
4H-SiC,” in Proceedings ISPSD, pp. 157–160, Jun.
2002.
[35] S. H. Ryu, S. Krishnaswami, M. O’Loughlin, J.
Richmond, A. Agarwal, J. Palmour, and A. R.
Hefner, “10-kV, 123-mΩ-cm2 4H-SiC power DMOSFETs,”
IEEE Electron Device Letters, vol. 25, no. 8, pp. 556–
558, Aug. 2004.
[36] Y. Sui, T. Tsuji, and J. A. Cooper, Jr., “On-State
Characteristics of SiC Power UMOSFETs on 115-μm Drift
Layers,” IEEE Electron Device Letters, vol. 26, no.
4, pp. 255-257, April 2005.
[37] Y. Sui, J. A. Cooper, and X. Wang, “Design,
simulation, and characterization of high-voltage SiC p-
IGBTs,” in Proceedings of ICSCRM, Otsu, Japan, Oct.
2007.
[38] Y. Sui, X. Wang, and J. A. Cooper, “High-Voltage Self-
Aligned p-channel DMOS-IGBTs in 4H-SiC,” IEEE
Electron Device Letters, vol. 28, no. 8, pp. 728–730,
Aug. 2007.
[39] Q. Zhang, C. Jonas, R. Callanan1, J. Sumakeris1, M.
Das, A. Agarwall, J. Palmourl, S.-H. Ryu, J. Wang, A.
Huang, “New Improvement Results on 7.5 kV 4H-SiC p-
IGBTs with Rdiff,on of 26 mΩ-cm2 at 250C,”
Proceedings of the 19th International Symposium on
Power Semiconductor Devices & ICs Jeju, Korea, pp281-
284, May 2007.
[40] Y. Li, P. Alexandrov, and J. H. Zhao, “1.88 mΩ-cm2
1650-V Normally on 4H-SiC TI-VJFET,” IEEE
Transactions on Electron Devices, vol. 55, no. 8, pp
1880-1886, Aug. 2008.
[41] J. Spitz, M. R. Melloch, J. A. Cooper, Jr., and M. A.
Capano, “2.6 kV 4H-SiC Lateral DMOSFET’s,” IEEE
Electron Device Letters, vol. 19, no. 4, pp100-102,
April 1998.
[42] J. A. Appels and H. M. J. Vas, “High Voltage Thin
Layer Devices (RESURF De-vices),” IEDM Technical
Digest, pp. 238, 1979.
[43] N. S. Saks, S. S. Mani, A. K. Agarwal, and M. G.
Ancona, “A 475-V High-Voltage 6H-SiC Lateral
MOSFET,” IEEE Electron Device Letters, vol. 20, no.
8, pp 431-433, Aug. 1999
[44] S. Banerjee, K. Chatty, T. P. Chow, and R. J.
Gutmann, “ Improved High-Voltage Lateral RESURF
MOSFETs in 4H-SiC,” IEEE Electron Device Letters,
vol. 22, pp. 209–211, May 2001.
[45] S. Banerjee, T. P. Chow, and R. J. Gutmann, “1300-V
6H-SiC Lateral MOSFETs With Two RESURF Zones,” IEEE
Electron Device Letters, vol. 23, no. 10, pp. 624-626,
Oct. 2002
[46] M. Noborio, J. Suda, and T. Kimoto, ”4H–SiC Lateral
Double RESURF MOSFETs with Low ON Resistance”, IEEE
Transactions on Electron Devices, vol. 54, no. 5,
pp.1216-1223, May 2007.
[47] T. Kimoto, H. Kosugi, J. Suda, Y. Kanzaki, and H.
Matsunami,”Design and Fab-rication of RESURF MOSFETs
on 4H-SiC(0001), (11-20), and 6H-SiC(0001)”, IEEE
Transactions on Electron Devices, vol. 52, no. 1,
pp.112-117, Jan. 2005
[48] C.-F. Huang, J.-R. Kuo, and C.-C. Tsai, “High Voltage
(3130 V) 4H-SiC Lateral p-n Diodes on a Semi-insulating
Substrate,” IEEE Electron Device Letters, vol. 29,
no. 1, pp83-85, Jan. 2008

[49] A. O. Konstantinov, Q. Wahab, N. Nordell, and U.
Lindfelt, "Ionization rates and critical field in 4H
silicon carbide," Applied Physics Letters, vol. 71,
pp. 90-92, 1997
[50] A. W. Ludikhuize, “A Review of RESURF Technology”,
ISPSD 2000, pp.11-18
[51] M. Imam, M. Quddus, J. Adams, and Z.
Hossain, “Efficacy of Charge Sharing in Reshaping the
Surface Electric Field in High-Voltage Lateral RESURF
Devic-es”, IEEE Transactions on Electron Devices,
vol. 51, no. 1, pp. 141-148, Jan. 2004.
[52] H. Wang, E. Napoli, and F. Udrea, “ Breakdown Voltage
for Super-junction Pow-er Devices With Charge
Imbalance: An Analytical Model Valid for Both Punch
Electron Devices, vol. 56, no. 12, pp. 3175-3183, Dec.
2009
[53] M.A. Capano, R. Santhakumar, R. Venugopal, M.R.
Melloch, and J.A. Cooper, Jr., “Phosphorus
Implantation into 4H-Silicon Carbide,” Journal of
Electronic Materials, vol. 29, no. 2, 2000.
[54] Y. Negoro, T. Kimoto, and H. Matsunami, “Electrical
Activation of High-Concentration Aluminum Implanted in
4H-SiC,” Journal of Applied Physics, vol. 96, no 9,
Nov. 2004
[55] T. Hiyoshi and T. Kimoto, “Elimination of the Major
Deep Levels in n- and p-Type 4H-SiC by Two-Step
Thermal Treatment,” Applied Physics Express 2 no.
091101, 2009
[56] Y. Negoro, K. Katsumoto, T. Kimoto, and
Matsunami, ”Electronic behaviors of high-dose
phosphorus-ion implanted 4H-SiC(0001),“ Journal of
Applied Physics, vol. 96, no.1, 2004.
[57] A. J. Lelis, D. Habersat , R. Green1, and N.
Goldsman, “Temperture-Dependence of SiC MOSFET
Threshold-Voltage Instability,” Materials Science
Forum, vol. 600-603, pp 807-810, 2009.
[58] A. Bellaouar, “Low-Power Digital VLSI Design,”
Toppan Company(s) PTE Ltd., 1995
[59] J. Baliga, “Power Semiconductor Devices,” PWS
Company, 1995
[60] C. F. Huang, C. L. Kan, T. L. Wu, M. C. Lee, Y. Z.
Liu, K. Y. Lee, and F. Zhao, “3510-V 390 mΩ-cm2 4H-
SiC Lateral JFET on a Semi-Insulating Substrate,”
IEEE Electron Device Letters, vol. 30, no. 9, pp 956-
959, Sep. 2009
[61] A. Valletta, P. Gaucci, L. Mariucci, A. Pecora, M.
Cuscunà, L. Maiolo, and G. Fortunato, “Threshold
Voltage in Short Channel Polycrystalline Silicon Thin
Film Transistors: Influence of Drain Induced Barrier
Lowering and Floating Body Effects,” Journal of
Applied Physics, vol. 107, no. 7, pp. 074 505-1–074
505-9, Apr. 2010.
[62] R. Singh, S.-H. Ryu, D. C. Capell, and J. W.
Palmour, “High Temperature SiC Trench Gate p-
IGBTs, ”IEEE Transactions on Electron Devices, vol.
50, no. 3, pp774-784, Mar. 2003
[63] P. B. Klein, “Carrier Lifetime Measurement in n- 4H-
SiC Epilayers,” Journal of Applied Physics, vol. 103,
no. 033702, 2008