簡易檢索 / 詳目顯示

研究生: 劉桓妤
Liu, Huan-Yu
論文名稱: Application Behavior-aware Flow Control in Network-on-Chip
指導教授: 金仲達
King, Chung-Ta
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年: 2010
畢業學年度: 98
語文別: 英文
論文頁數: 37
中文關鍵詞: 晶片網路流量控制擁塞控制流量預測
外文關鍵詞: network-on-chip, flow control, congestion control, traffic prediction
相關次數: 點閱:2下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • Multicore might be the only solution when concerning about performance and power issues in future chip processor architecture. As the number of cores on a chip keeps on increasing, traditional bus-based architectures are incapable of offering the required communication bandwidth on the chip, so Network-on-chip (NoC) becomes the main paradigm for on-chip interconnection. NoCs not only offer significant bandwidth advantages but also provide outstanding flexibility. However, the performance of NoCs can be degraded significantly if the network flow is not controlled properly. Most previous solutions try to detect network congestion by monitoring the hardware status of the network switches or links. Change of hardware statuses at local end may indicate possible congestions in the network, and thus packet injection into the network should be controlled to react to the congestions. The problem with these solutions is that congestion detection is based only on local status without global information. Actual congestions may occur somewhere else and can only be detected through backpressure, which may be too passive and too slow for taking reactive measures in time.
    This work takes a proactive approach for congestion detection. The idea is to predict the changes in global, end-to-end network traffic patterns of the running application and take proactive flow control actions to avoid possible congestions. Traffic prediction is based on our recent paper [1], which uses a table-driven predictor for predicting application communication patterns. In this thesis, we discuss how to use the prediction results for effective scheduling of packet injection to avoid network congestions and improve the throughput. The proposed
    scheme is evaluated using simulation based on a SPLASH-2 benchmark as well as synthetic traffic. The results show its superior performance improvement and negligible execution overhead.


    當考慮到在將來的晶片處理器架構的效能跟電的議題時,多核心可能是唯一的解決方法。當晶片上的核心數量一直不斷增加時,傳統的以匯流排為主的架構已經不能滿足晶片上需要的傳輸頻寬,而晶片網路(NoC)就成為晶片上互連傳輸的主流。晶片網路不只提供可觀的頻寬的優點,也展現出它很傑出的彈性。然而,假如網路的流量不能被適當的控管晶片,網路效能會大大的降低。大部份以前的解法是藉著偵測網路上的交換器跟連結的硬體狀態嘗試去偵測網路擁塞。這些局部端點的硬體狀態的改變可以指出網路上可能會發生的壅塞,再藉由壅塞的狀態去控制網路的封包注入。這些偵測網路壅塞的方法是只有看局部的硬體狀態,並沒有考慮整個網路的情況,實際上網路的壅塞不是只會發生在局部的地方,而是可能會發生在網路的其他地方。而且用硬體狀態偵測網路壅塞的方法,是一種回壓的機制,這是一個很被動也太慢的方法,並不能及時的反應真正的網路壅塞。
    這篇論文就採用一個比較前瞻性的方法來偵測網路壅塞。概念就是去預測正在執行的應用程式的網路流量模型,這是一種看總體網路的點對點傳輸的方式,藉由這個預測方法做流量控制來避免網路壅塞。網路流量的預測是以一篇最近的論文當作基礎,它的手法是用表來紀錄應用程式傳輸模型而達到預測的目的。在這篇論文,我們討論到如何用這些預測出來的結果來做有效的封包注入的行程,以避免網路壅塞而且也能提高總體的處理能力。我們提出的這個系統是使用SPLASH-2來評估我們的模擬,另外也用了合成的網路流量來作實驗。這些實驗
    結果可以看出我們大大的增進整體的效能,而且總體執行時間也有些微的減少。

    1 Introduction 1 2 Motivating Example 6 3 Related Work 10 4 Problem Formulation 12 4.1 Application-Driven Predictor . . . . . . . . . . . . . . . . . . . . . . 14 5 Traffic Control Algorithm 19 5.1 Traffic Control Algorithm and Implementation Overhead . . . . . . 19 5.2 Data Aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 Area Occupancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 Experimental Results 25 6.1 Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 Real Application Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 Synthetic Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 Conclusion and Future Works 32

    [1] Y. S.-C. Huang, C.-K. Chou, C.-T. King, and S.-Y. Tseng, “Ntpt: On the
    end-to-end traffic prediction in the on-chip networks”, in Proc. 47th ACM
    IEEE Design Automation Conference, 2010.
    [2] S. Bell, B. Edwards, J. Amann, R. Conlin, K. Joyce, V. Leung, J. MacKay,
    M. Reif, Liewei Bao, J. Brown, M. Mattina, Chyi-Chang Miao, C. Ramey,
    D. Wentzlaff, W. Anderson, E. Berger, N. Fairbanks, D. Khan, F. Montenegro,
    J. Stickney, and J. Zook, “Tile64 - processor: A 64-core soc with mesh
    interconnect”, in Proc. Digest of Technical Papers. IEEE International
    Solid-State Circuits Conference ISSCC 2008, Feb. 3–7, 2008, pp. 88–598.
    [3] Jose Duato, Sudhakar Yalmanchili, and Lionel Ni, “Interconnection networks”,
    2002, pp. 428–431.
    [4] S. Mascolo, “Classical control theory for congestion avoidance in high-speed
    internet”, in Proc. Decision and Control Conference, 1999.
    [5] Cui-Qing Yang, “A taxonomy for congestion control algorithms in packet
    switching networks”, in IEEE Network, 1995.
    [6] Hua Yongru Gu, Wang Hua O., and Hong Yiguang, “A predictive congestion
    control algorithm for high speed communication networks”, in Proc.
    American Control Conference, 2001.
    [7] Erland Nillson, Mikael Millberg, Johnny ぴOberg, and Axel Jantsch, “Load
    distribution with the proximity congestion awareness in a network on chip”,
    in Proc. Design, Automation, and Test in Europe, 2003, p. 11126.
    [8] U. Y. Ogras and R. Marculescu, “Prediction-based flow control for networkon-
    chip traffic”, in Proc. 43rd ACM IEEE Design Automation Conference,
    2006, pp. 839–844.
    [9] U. Y. Ogras and R. Marculescu, “Analysis and optimization of predictionbased
    flow control in networks-on-chip”, in ACM Transactions on Design
    Automation of Electronic Systems, 2008.
    [10] Vincent Nollet, Th´eodore. Marescaux, and Diederik Verkest, “Operatingsystem
    controlled network on chip”, in Proc. 41st ACM IEEE Deaign
    Automation Conference, 2004.
    [11] P. Avasare, J-Y. Nollet, D. Verkest, and H. Corporaal, “Centralized endto-
    end flow control in a best-effort network-on-chip”, in Proc. 5th ACM
    internatinoal conference on Embedded software, 2005.
    [12] Mohammad S. Talebi, Fahimeh Jafari, and Ahmad Khonsari, “A novel
    congestion control scheme for elastic flows in network-on-chip based on sumrate
    optimization”, in ICCSA, 2007.
    [13] M. S. Talebi, F. Jafari, and A. Khonsari, “A novel flow control scheme
    for best effort traffic in noc based on source rate utility maximization”, in
    MASCOTs, 2007.
    [14] Mohammad S. Talebi, Fahimeh Jafari, Ahmad Khonsari, and Mohammad H.
    Yaghmaeem, “Best effort flow control in network-on-chip”, in CSICC, 2008.
    [15] Fahimeh Jafari, Mohammad S. Talebi, Mohammad H. Yaghmaee, Ahmad
    Khonsari, and Mohamed Ould-Khaoua, “Throughput-fairness tradeoff in
    best effort flow control for on-chip architectures”, in Proc. 2009 IEEE
    International Symposium on Parallel and Distributed Processing, 2009.
    [16] T. Marescaux, A. R˚angevall, V. Nollet, A. Bartic, and H. Corporaal, “Distributed
    congestion control for packet switched networks on chip”, in
    ParCo, 2005.
    [17] J.W. van den Brand, C. Ciordas, K. Goossens, and T. Basten, “Congestioncontrolled
    best-effort communication for networks-on-chip”, in Proc. Design,
    Automation, and Test in Europe, 2007.
    [18] Jin Yuho, Yum Ki Hwan, and Kim Eun Jung, “Adaptive data compression
    for high-performance low-power on-chip networks”, in Proc. 41st annual
    IEEE/ACM International Symposium on Microarchitecture, 2008.
    [19] Keshav Srinivasan, “Congestion control in computer networks”, 1991.
    [20] Vassos Soteriou, Hangsheng Wang, and Li-Shiuan Peh, “A statistical traffic
    model for on-chip interconnection networks”, in Proc. 14th IEEE International
    Symposium on Modeling, Analysis, and Simulation, 2006.
    [21] Anthony Leroy, “Optimizing the on-chip communication architecture of low
    power systems-on-chip in deep sub-micron technology”, 2006.
    [22] N. Agarwal, T. Krishna, L. Peh, and N. Jha, “Garnet: A detailed on-chip
    network model inside a full-system simulator”, in Proceedings of International
    Symposium on Performance Analysis of Systems and Software,
    2009.

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE