應用於微波超寬頻汽車雷達之CMOS發射器及鎖相迴路設計

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研究生：	譚凱文 Kai, Wen Tan
論文名稱：	應用於微波超寬頻汽車雷達之CMOS發射器及鎖相迴路設計 Design of Transmitter and Phase-locked Loop in CMOS for Microwave Ultra-wideband Automotive Radar Applications
指導教授：	徐碩鴻 Hsu, Shawn S.H. 朱大舜 Chu, Ta-Shun
口試委員:	謝協宏朱大舜孟慶宗黃國威
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2015
畢業學年度：	103
語文別：	英文
論文頁數：	89
中文關鍵詞：	汽車雷達、超寬頻脈波、脈波壓縮、鎖相迴路、CMOS發射器、K頻帶
外文關鍵詞：	Automotive radar, UWB pulse, pulse compression, PLL, CMOS TX, K band
相關次數：	點閱：4 下載：0
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本論文主要呈現於不同汽車防撞雷達規格中，實現兩顆K頻段發射機晶片和一顆W頻段寬頻操作的鎖相迴路晶片。這些電路將以CMOS製程技術製作，達到低價、高整合度並符合預期的功能。
首先，一個K頻段超寬頻脈波壓縮之汽車防撞雷達發射器以90 nm CMOS呈現，其中包含脈波產生器、混頻器、驅動放大器，鎖相迴路和時脈電路。具有數位編碼的脈波壓縮技術可以有效的提升解析度同時也改善訊雜比。我們提出的發射器可以快速且精準的產生編碼，且有低功率和小面積操作，並具有可程式化能力。相較於先前文獻所提出具有簡單編碼技術的超寬頻脈波雷達，本次所提出的發射器設計了高速移位暫存器，進一步達到15位元偽雜訊編碼且可使整體系統訊雜比提升至23.5分貝。量測結果驗證了正確的輸出波型且具有不同的編碼，並符合FCC所致定的規範，具有超過3Gb/s的調變速率(脈波重複頻率為6.125 MHz)，解析度可達到5公分。
第二顆電路改善了上一版的K頻段超寬頻雷達之發射器。在這次設計中提出了頻寬延展和脈波整型技術更進一步改善先前所提出的發射器，將原本的不歸零編碼替換成歸零編碼到壓縮脈波之中，輸出脈波之頻寬可以提升至兩倍，更可改變在雷達系統之中的解析度。接著，脈波整型技術使用了可調頻寬之低通濾波器，脈波整型技術可以壓抑輸出頻譜上的旁瓣之最大值，使整體壓縮脈波頻譜在提升雷達訊雜比之下，可以更符合FCC遮罩規範。並減少可調變率1.5Gb/s(相較於先前的工作少了一半的速率)，整體解析度同樣可達到5公分，而脈波整型也可以壓抑5分貝的旁瓣功率。
最後實現了一顆90 nm CMOS W頻帶寬頻操作的鎖相迴路，本次設計中提出了一種新穎的乘三頻率的技術，僅需要兩顆共振腔還有單一交互耦合對即可完成倍頻輸出且寬頻調整特性之壓控式震盪器，達到低功率操作。鎖相迴路之鎖定範圍在主頻率可達25.4-29.7 GHz，且在三倍諧波可獲得12.9 GHz (從76.2到89.1 GHz, 15.6%)的可調整範圍，當供應電壓為1.2伏特之下(功率消耗為62.4 mW)，鎖相迴路之閉迴路相位雜訊之量測結果為-83.5 dBc/Hz在78.34 GHz，相較於目前文獻中，本次所提出的寬頻鎖相迴路是目前CMOS 鎖相迴路於相近操作頻率中達到最大可調頻寬的成果。

This dissertation presents two K-band transmitter front-ends and a W-band wide tuning range PLL for automotive radar applications with different standards. These circuits are all implemented in CMOS technology aiming for low cost, high integration level, and desired functionality.
First, a K-band ultra-wideband (UWB) pulse-compression (PC) automotive radar transmitter in 90 nm CMOS is presented, which is composed of the fully-integrated pulse generator, mixer, driver amplifier, phase-locked loop (PLL), and timing circuitry. The PC technique with coding gain can effectively enhance the detection resolution and also improve the signal-to-noise ratio. We propose a PC transmitter allowing fast and precise code generation with small power consumption and chip area, and also offering reconfigurable capability. Compared with previously reported UWB pulse radars with relatively simple coding schemes, the proposed transmitter features a much more challenging 15-bit pseudo noise (PN) code design using high speed shift registers, which can improve signal-to-noise ratio (SNR) up to 23.5 dB. The measured results demonstrate correct output waveforms corresponding to different modulation codes with the spectrum well confined under the regulation mask. With a modulation rate over 3 Gb/s (pulse repeat frequency of 6.125 MHz), a resolution of ~ 5 cm can be achieved.
Second, a K-band UWB PC automotive radar transmitter modified based on the first work is presented. This design proposes the bandwidth extension and pulse shaping techniques to further improve the performance of the transmitter. The conversion of non-return zero (NRZ) to return zero (RZ) signal format is performed in each bits of compressed pulse. The bandwidth of the output pulse can be doubled, leading to increased resolution of radar systems. Besides, a pulse shaping technique is employed based on an adjustable low-pass filter. The pulse shaping technique can reduce the peak power of side lobe of the PC pulse to satisfy the FCC mask regulation and also enhance the spectrum efficiency. The output spectrum of PC pulse will be well-confined in the FCC mask to improve the SNR of the radar system. Under the a reduced modulation rate of 1.5 Gb/s (only half rate compared with that in the first work), a same resolution of ~ 5 cm can be achieved. Also, the proposed pulse shaping can reduce the peak power of side lobe by 5 dB.
Finally, a wide tuning range W-band phase-locked loop (PLL) in 90 nm CMOS is presented. A novel frequency tripling topology with a single cross-coupled pair and a dual tank is proposed for the voltage-controlled oscillator (VCO) to achieve wide tuning characteristics under low power consumption. The locking range of the PLL at the fundamental tone is 25.4–29.7 GHz, and an excellent tuning range at the third harmonic frequency up to 12.9 GHz (from 76.2 to 89.1 GHz, 15.6%) is obtained. Under a 1.2 V supply voltage (Pdiss= 62.4 mW), the measured closed-loop phase noise of the PLL is 83.5 dBc/Hz at 78.34 GHz. To the best of our knowledge, the achieved turning range is the highest currently reported for the PLLs operating in a similar frequency range in CMOS technology.

致謝………………………………………………………………………………...…………..i
摘要………………………………..……………..…………………………………………...iii
Abstract……………………………………………………….……………………………….v
Contents……………………………………………………………………………………...vii
Table of Figures..……………………………………………………………………………...x
Table of Tables..……………………………………………………………………………..xiv
Publication List……………………………………………………………………………...xv
CHAPTER I INTRODUCTION    1
1 Background and motivation    1
2 Organization of dissertation    4
CHAPTER II BASIC PRINCIPLES OF AUTOMOTIVE RADARS    5
1 Radar system    5
2 Continuous-wave (CW) radar    6
2.1 Frequency-modulated continuous-wave radar    8
2.2 Pseudo-noise code radar    9
3 Ultra-wideband pulse radar    10
4 Pulse compression technique    12
4.1 Analog pulse compression    13
4.2 Digital pulse compression    15
5 Summary and conclusion    21
CHAPTER III A RECONFIGURABLE PULSE-COMPRESSION AUTOMOTIVE RADAR TRANSMITTER IN 90 NM CMOS    22
1 Introduction    22
2 Transmitter architecture    24
2.1 Proposed the transmitter architecture    25
2.2 System specification    27
3 Circuit design    30
3.1 Reconfigurable Pulse Generator    30
3.2 High Speed Shift Registers    32
3.3 Mixer and Driver Amplifier    34
3.4 Phase-locked loop    37
4 Experimental results    39
5 Summary and Conclusion    43
CHAPTER IV A K-BAND UWB PULSE COMPRESSION TRANSMITTER WITH BANDWIDTH EXTENSION AND PULSE SHAPING TECHNIQUES    45
1 Introduction    45
2 Transmitter architecture    46
3 Circuit design    52
4 Experimental results    57
5 Summary and Conclusion    62
CHAPTER V A WIDE TUNING RANGE W-BAND PLL USING THE FREQUENCY TRIPLING TECHNIQUE.    64
1 Introduction    64
2 PLL design    65
3 FT-VCO design    67
4 Design of other building blocks    73
4.1. Divider Chain    73
4.2. Phase Frequency Detector and Charge Pump    74
4.3. Loop filter    75
5 Experimental results    78
5 Summary and Conclusion    83
CHAPTER VI CONCLUSION    84
REFERENCES    86

                                

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