應用於單通量量子電路且考量時鐘樹的新型擺置演算法

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研究生：	王勁程 Wang, Ching-Cheng
論文名稱：	應用於單通量量子電路且考量時鐘樹的新型擺置演算法 A Novel Clock Tree Aware Placement Algorithm for Single Flux Quantum Logic Circuits
指導教授：	麥偉基 Mak, Wai-Kei
口試委員:	王廷基 Wang, Ting-Chi 陳宏明 Chen, Hung-Ming
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2021
畢業學年度：	109
語文別：	英文
論文頁數：	34
中文關鍵詞：	標準元件擺置、實體設計、時鐘樹合成、超導電路
外文關鍵詞：	Placement, Physical Design, Clock Tree Synthesis, Superconducting Circuit
相關次數：	點閱：4 下載：0
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在單通量量子電路中,幾乎所有電路元件都需要接收時鐘信號,這會導致很的高時鐘網路繞線成本。此外,單通量量子電路的時鍾樹需要在每個樹分支節點插入時鐘分離器元件,這使得針對傳統的電路擺置設計流程和時鍾樹合成無效,導致無法獲得具有低時鐘偏斜的高質量時鍾樹。為了解決這些問題,我們提出了一種兩階段全局擺置方法和擺置合法化後的擺置優化演算法。我們的兩階段全局擺置方法首先應用傳統的全局擺置演算法將電路元件均勻地放置在給定的單通量量子電路設計中,接著進行時鍾樹合成和時鐘分配器插入,然後同時針對原始電路元件和時鐘分配器執行第二次全局擺置。在第二次全局擺置階段中,使用前瞻性合法化技術來擴散原始電路元件和時鐘分離器,並多次重新合成時鍾樹以獲得優化的時鍾樹拓撲,使得原始電路元件與時鐘分配器的重疊減少。此外,我們也同時優化了數據信號和時鐘信號的總線長。在所有單元的擺置合法化後,我們的擺置優化方法可以運行以進一步減少時鐘偏斜。與之前最先進的工作相比,我們平均可以將總半週線長度和時鐘偏斜分別減少 17% 和 30%。

In a single-flux-quantum (SFQ) circuit, almost all cells need to receive the clock signal which incurs a high clock routing overhead. Besides, the clock tree of a SFQ circuit requires the insertion of a clock splitter cell at every tree branching point which renders the conventional design flow of placement followed by clock tree synthesis ineffective to obtain a high quality clock tree with low clock skew. To address these issues, we propose a two-stage global placement methodology and a placement refinement algorithm after placement legalization. Our two-stage global placement methodology first applies a conventional global placement algorithm to place the cells in the given SFQ circuit evenly, which is followed by clock tree synthesis and clock splitter insertion, and then performs a second stage of global placement to re-place both the original cells and clock splitters at the same time. In the second global placement stage, the look-ahead legalization technique is used to spread out the original cells and the clock splitters, and the clock tree is re-synthesized several times to obtain an optimized clock tree topology such that there are little overlaps of the clock splitters with the original circuit cells. In addition, the total wirelength of data signals and clock signal is optimized concurrently. After legalizing the placement of all cells, our placement refinement method can be run to further reduce the clock skew. Compared with the previous state-of-the-art work, on average we can reduce the total half-perimeter wirelength and clock skew by 17% and 30%, respectively.

誌謝 ii
摘要 iii
Abstract iv
Contents v
List of Figures vii
List of Tables ix
Introduction 1
1 Advantages of SFQ Logic Circuits.............................. 1
2 Challenges of SFQ Logic Circuits Placement.................... 1
3 Motivation and Contribution .................................. 2
4 Organization ................................................. 4
Preliminaries 5
1 Placement .................................................... 5
2 Clock Tree Synthesis ......................................... 6
3 Prior Works .................................................. 6
Proposed Approach 9
1 Algorithm Outline............................................ 10
2 Modified Bound-To-Bound (B2B) [15] Net Model ................ 11
3 Trial Global Placement without Clock Splitters (1st GP) & Trial Clock Tree Synthesis............................................. 12
4 Update Netlist with Clock Splitters & Clock Nets............. 12
5 Global Placement of All Cells Including Clock Splitters & Clock Tree Re Synthesis (2nd GP........................................ 13
6 Placement Refinement ........................................ 18
Experimental Results 23
1 Experimental Setup .......................................... 23
2 Benchmark Generation......................................... 23
3 Differences between Proposed Approaches and Enhanced-MILP ... 25
4 The Algorithm Flow of Enhanced-MILP ......................... 27
5 Results on ISCAS’85 Benchmark Suite ......................... 27
Conclusion 32
References 33

                                

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