性電子產品的多元化發展，半導體產業的需求端已經大量的膨脹，許多半導體界廠商，莫不持續改進製程、縮短製造時間、提高良率，以期在半導體產業的競爭中超越其他廠商搶下訂單。而在製造流程複雜，且生產週期時間長的的晶圓製造廠中，生產週期時間、產出量、機台利用率等重要指標，均與在製品存貨(Work In Process, WIP)有密切關聯。過去的研究也證明若維持適當在製品存貨水準，便能兼顧最大產出量與最短生產週期時間。而限制理論中提出瓶頸工作站為系統產出的限制，必須掌握瓶頸並分析其限制，才能使系統的產出達到預期。因此本研究發展瓶頸工作站與全廠的在製品水準設定之方法，藉由倒傳遞類神經網路找出瓶頸工作站，針對不同的瓶頸工作站發展設定全廠在製品水準的方法，以確保在最大產出前提下，維持最低的全廠在製品水準。

亦強調非瓶頸機台必須配合瓶頸機台，以避免瓶頸機台前的等候線中沒有在製品的情形發生，然而一個晶圓廠機台種類繁多，如何辨認哪一些才是關鍵非瓶頸機台，對於有效管理晶圓廠是個重要的課題。本研究考量瓶頸漂移的情況下，以決策樹演算法找出與瓶頸工作站強烈相關的上游非瓶頸機台，並分析這些關鍵非瓶頸機台如何影響瓶頸工作站的在製品水準。最後再應用倒傳遞類神經網路探討瓶頸機台與關鍵非瓶頸機台相關影響變數與全廠在製品水準的關係，藉以設定理想的全廠在製品水準，並發展控管與調整的方法，讓管理者只需要聚焦於瓶頸工作站及其上游關鍵機台，便得以用最低全廠在製品水準來維持瓶頸站之安全在製品水準，以達到全廠最大產出。

In a wafer fabrication facility (fab), cycle time, throughput, and utilization are strongly related to work-in-process (WIP). Past researchers have proved that maintaining a suitable number of WIP can get the maximum throughput and the minimum cycle time. Therefore, WIP is one of the most important performance indices in a fab.

Based on the Theory of Constraints, managing bottleneck workstations is important for controlling the throughput of a system. In this study, we use the artificial neural network to find bottleneck workstations in a fab, and set their suitable WIP levels. A decision tree model is used to identify important non-bottleneck upstream workstations that are strongly related to bottleneck workstations, and then their influence on the bottleneck workstations are analyzed. Then some artificial neural network models for analyzing the WIP levels of bottleneck workstations and the total WIP in a fab are developed. These models can provide managers useful information for setting the suitable total number of WIP to maintain the required WIP levels for the bottleneck workstations and adjusting key non-bottleneck upstream workstations to reduce the total WIP level.

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