A common practice to evaluate the network-on-chip (NoC) of a chip-multiprocessor (CMP) is to use trace-driven simulation. Execution traces of benchmark programs are first generated by some real machines or emulators. They are then fed into an NoC simulator that simulates the NoC of the CMP under study to produce performance results. If there is a need to evaluate the NoC under different number of cores, it is common to generate one trace file for each number of cores. The efforts to generate these trace files and the space to store them are often excessive. Of course, it is possible to merge traces of a larger number of cores to produce traces of a smaller number of cores. However, since traces do not preserve causality relationship of the execution, the synthesized traces often result in larger errors in evaluation.

To obtain more accurate evaluation results for NoC of different number of cores, we adopt in this thesis the intermediate representation (IR) \cite{willy2011} to record the execution traces and their causality relationship and propose to generate traces of different numbers of cores by synthesizing IR of a smaller number of cores from that of a larger number of cores. The synthesis method merges IR events from different cores and provides a causality-based reordering scheme to produce a new IR for a different number of cores. Our evaluation shows that synthetic traces from the proposed synthesis method can achieve similar performance results as using real traces.

一般用追蹤驅動模擬的方式來評估多核心晶片上的網路效能，通常在特定的機器或仿真器下跑程式去產生相對應的追蹤驅動模擬的追蹤檔。追蹤檔可以提供追蹤驅動模擬去評估晶片網路上的效能，但若要模擬不同核心數的晶片網路則必須在相對應的核心數的機器，得到所需要的追蹤檔。通常來說，產生追蹤檔的過程需要很多時間和心力才能得到，我們也可以去合併一般的追蹤檔，來產生相對應核心數所需的追蹤檔。但是，一般的追蹤檔並沒有程式因果關係的資訊，合併一般的追蹤檔會與實際程式行為有很大的誤差存在。
　　在不同的核心數下，為了獲得更準的模擬評估結果，我們利用了因果感知中介表示法(IR)去記錄程式行為的因果關係，再將此因果感知中介表示(IR)轉成追蹤檔，且更進一步，在這篇論文我們提出了一個工具，利用較多核心數下的程式因果感知中介表示(IR)去合成較少核心數的程式因果感知中介表示(IR)。此方法主要是去合併不同核心上發生的因果感知中介表示(IR)事件且提供一個以維持因果順序為基準的重排演算法，目的在於合成較小核心數時，整個程式的因果關係能夠維持。在實驗中，本論文提出的方法能夠讓合成出來的追蹤檔在晶片網路效能評估上，具備和真實情況下的追蹤檔相似的效能評估結果。

[1] Hsiang-Wei Lo, “Causality-aware intermediate representation for trace-driven simulation of network-on-chip”, Master Thesis, Department of Computer Science, National TsingHua University, Hsinchu, Taiwan 30013, R.O.C., July 2011.
[2] R.R. Schaller, “Moore’s law: past, present and future”, Spectrum, IEEE, 1997.
[3] Juha-Pekka Soininen Martti Forsell Mikael Millberg Johny Oberg Kari Tiensyrja Shashi Kumar, Axel Jantsch and Ahmed Hemani, “A network on chip architecture and design methodology”, Proceedings of IEEE Computer Society Annual Symposium on VLSI, 2002.
[4] Shashi Kumar Adam Postula Johnny Oberg Mikael Millberg Dan Lindqvist Ahmed Hemani, Axel Jantsch, “Network on a chip: An architecture for billion transistor era”, In Proceeding of the IEEE NorChip Conference, November 2000.
[5] Peter S. Magnusson, Magnus Christensson, Jesper Eskilson, Daniel Forsgren, Gustav Hallberg, Johan Hogberg, Fredrik Larsson, Andreas Moestedt, and Bengt Werner, “Simics: A full system simulation platform”, Computer, vol. 35, pp. 50–58, 2002.
[6] Li Shang, Li-Shiuan Peh, and Niraj K. Jha, “Dynamic voltage scaling with links for power optimization of interconnection networks”, Proceedings of International Symposi High-Performance Computer Architecture, International Symposium on, vol. 0, pp. 91, 2003.
[7] Peter C. Fishburn, “Intransitive indifference with unequal indifference intervals”, Journal of Mathematical Psychology, vol. 7, pp. 144–149, February 1970.
[8] Joel L. Wolf, Harold S. Stone, and Dominique Thiebaut, “Synthetic traces for tracedriven simulation of cache memories”, IEEE Trans. Comput., vol. 41, pp. 388–410, April 1992.
[9] Derek R. Hower and Mark D. Hill, “Rerun: Exploiting episodes for lightweight memory race recording”, SIGARCH Comput. Archit. News, vol. 36, pp. 265–276, June 2008.
[10] Matthew Farrens Venkatesh Akella Christopher Nitta, Kevin Macdonald, “Inferring packet dependencies to improve trace based simulation of on-chip networks”, Proceedings of 2011 Fifth IEEE/ACM International Symposium on Networks on Chip (NoCS), 2011.