隨著晶片製成的發展，不同種類的整合封裝技術相繼被提出，例如利用矽中介板或嵌入式多晶片互聯橋的2.5D封裝技術，或是利用堆疊方式的3D封裝技術。但是這些技術都各有優缺點，例如堆疊封裝雖然縮小晶片面積但伴隨著散熱問題，或是2.5D技術難以使晶片面積縮小等。因此我們希望有一個高效率的方法能對不同的晶片設計來產生一個異質結構已提高晶片設計之效能。
在本論文中，我們首先考慮各種不同的整合技術和其優缺點、製造限制與成本。我們考慮的整合技術為上述所提到的，其這些技術所包含的載體有印刷電路板、封裝基板、矽中介板、嵌入式多晶元互聯橋和集成扇出。我們提出一個效能導向的多晶片整合方法其能夠用不同的載體結合出異質整合結構。我們提出了一個結合強化式學習模型與模擬退火的方法，該方法包含兩大部分，第一部分是訓練一個強化式學習模型來建構出一個載體結構，第二部分為利用一個模擬退火演算法對建構出來的載體結構做晶片位置的分配。當晶片位置分配結束後評估該結果效能如何並回傳給模型進行模型的更新。
我們的實驗結果說明了我們提出的方法在效能方面優於現有的方法，而在時間方面在較大晶片設計下耗時縮短6倍以上的時間。

Along with the revolution of IC design, advanced integration technologies for multiple dies have been proposed by packaging and manufacturing companies. For instance, silicon interposer and embedded silicon bridge are two kinds of 2.5D technologies to integrate multiple dies. Besides 2.5D integration, 3D integration is another advanced technology by vertically stacking dies. However, there are some pros and cons for each technology. Therefore, we aim to propose a method that integrates multiple dies with different package technologies to achieve high performance.

In this thesis, we adopt different kinds of multi-die integrations technologies in our problem. Additionally, we also consider their manufacturing constraints and costs. The carriers from these integration technologies can include printed circuit board (PCB), package substrate, interposer, and silicon bridge. We propose a performance-driven integration methodology that aims to generate a high-performance carrier structure and a die assignment with respect to the structure. This methodology combines a reinforcement learning (RL) network and a simulated annealing (SA) algorithm, by training the network to modify the carrier structure and using SA to do die assignments for the structure. The experimental results show that our methodology outperforms a previous work.

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