在本篇論文中, 我們對於高效能的有限脈衝反應濾波器設計(FIR filter design)提供了一個時間導向架構(Timing-Driven Architecture)以及模組選擇方法(Component Selection Method). 我們研發了一個FIR產生器, 它可以藉由決定符合使用者所下的時間限制的FIR結構(FIR Structure), 模組型式(Component Type) 以及延遲預算(Delay Budget) 來產生Verilog-based 的RTL設計. 藉由整合FIR產生器以及合成, 佈局等CAD工具, 我們針對高效能的FIR設計研發了一個設計環境. 我們的實驗結果證明了我們所提供的方法的有效.

In this thesis, we present a timing-driven architecture and component selection method for high-performance FIR designs. We develop an FIR generator that can generate Verilog-based RTL design specifications on the fly by determining FIR’s structure, component types and their delay budgets subject to satisfying the given timing constraints. By integrating the FIR generator and a number of commercial RTL/logic and physical synthesis tools, we develop a design environment for high-performance FIR designs. Experimental results are reported to demonstrate the effectiveness of our proposed method.

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