磁性隨機存取記憶體（MRAM）被視為在未來具有潛力可以取代現有的靜態隨機存取記憶體（SRAM）、動態隨機存取記憶體（DRAM）及快閃記憶體（Flash memory）等等嵌入式和商用式記憶體。其同時具備了隨機存取記憶體及快閃記憶體的優點，因此在未來很有可能會被廣泛地應用在系統單晶片（System-On-Chip）上。而近幾年來，已有部分磁性隨機存取記憶體產品在市場上出現，但並不表示其測試相關的問題都已被完全解決。

為了確保磁性隨機存取記憶體產品的品質及良率，本論文針對該記憶體提出了「寫入干擾錯誤模型（Write Disturbance Fault Model）」。同時也針對磁性隨機存取記憶體發展出稱作RAMSES-M的錯誤模擬程式，可以利用它來建構寫入干擾錯誤模型的最短測試演算法及評估對應的錯誤覆蓋率。我們也針對此錯誤提出一特殊之偵測方式與對應之測試演算法。然而為了找出寫入干擾錯誤的錯誤原因，我們亦提出一「可適應診斷演算法（Adaptive Diagnosis Algorithm）」來進行錯誤診斷。藉由工研院電光所合作的磁性穿隧接面（Magnetic Tunneling Junction）元件模型，我們也建立了「翻轉式磁性隨機存取記憶體（Toggle MRAM）」陣列的SPICE電路模型，以獲得寫入干擾錯誤模型及其診斷方法的電路模擬結果。

此外，本論文也設計了一個具有寫入干擾錯誤診斷能力的內建式自我測試（Built-In Self-Test）電路；同時利用翻轉式磁性隨機存取記憶體的「寫入前先讀（Read-before-Write）」機制，來縮短整體的測試時間，針對1-Mbit磁性隨機存取記憶體所提出的內建式自我測試電路之硬體面積只佔該記憶體的0.05%。最後，我們也將所提出之測試演算法應用在實際晶片量測上，晶片量測結果可以驗證寫入干擾錯誤的存在，且本論文所提出之測試方法亦可以提高磁性隨機存取記憶體的錯誤偵測能力。

The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future.
The MRAM is fast and does not need a high supply voltage for Read/Write operations, and is compatible with the CMOS technology. It can also endure almost unlimited Read/Write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC.

In this thesis, we present the Write Disturbance Fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the Write operation. March tests have high coverage for conventional RAM faults; however, they do not detect
all WDFs. To improve quality and yield of MRAM, we propose a new test algorithm to detect WDF for MRAM in this thesis. The proposed test algorithm is a March-based one, i.e., it has linear time complexity and can easily be implemented with built-in self-test (BIST). We then present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. Furthermore, to enhance the ability of diagnosis, we propose an adaptive
diagnosis algorithm (ADA) that can efficiently identify the WDF for MRAM. However, the proposed test method can evaluate the process stability and uniformity using logical test method. We collaborated with EOL to construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results.

Additionally, we present a built-in self-test (BIST) circuit that supports the proposed WDF diagnosis test method. We propose the BIST scheme based on the Decision Write mechanism of the toggle MRAM to reduce total test time. Experimental results show that the fault coverage of proposed test algorithm is higher than that of traditional March test algorithms. Also, circuit simulation result justifies that the adaptive diagnosis algorithm is useful for diagnosis of a WDF cell. The proposed BIST circuit has only 0.05% of hardware overhead for a 1-Mbit MRAM, and
test time is further shortened for the toggle MRAM. Furthermore, the proposed WDF model is justified by chip measurement results. Finally, specific MRAM fault behavior and test issues are discussed.

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