本論文描述了一個應用於紅外線感測器陣列並擁有反向器架構式電容反饋跨阻抗放大器、像素內雙重關聯式取樣電路機制、以及虛多重取樣技術的讀出積體電路。本文使用反向器架構式電容反饋跨阻抗放大器配合耦合電容執行自動偏移電壓消除機制來消除隨著製程改變的偏移電壓，並以此架構來取代傳統的差動對式電容反饋跨阻抗放大器。在此架構中，可經由外部電壓源在曝光開始之前供給指定電壓，達到探測器偏壓的可調機制。這樣的構想不僅維持了探測器偏壓的均勻度、穩定性、以及訊號的注入效率，同時還能夠減少像素面積。在壓抑低頻率雜訊以及固定圖像雜訊時的訊號處理中，雙重關聯式取樣電路是十分有用的機制。相較於傳統的雙重關聯式取樣電路，本文所提出的像素內雙重關聯式取樣電路只需要一個電容以及一顆作為開關並連接外部電壓源的電晶體便可完成。此外，本論文採取了虛多重取樣技術來減少時間雜訊。虛多重取樣技術的雜訊消除能力與傳統多重取樣技術相比毫不遜色，並且不像傳統多重取樣技術一樣需要正比於取樣次數的讀出時間。
我們透過0.18微米的互補式金屬氧化物半導體製程技術，設計並製造了擁有55乘65像素陣列並搭載上述構想的讀出積體電路原型，並在3.3伏特的操作電壓之下透過量測來驗證所提出之電路的功能以及效能。量測驗證的結果為: 像素尺寸縮小至12微米乘12微米、72張的每秒顯示幀數、0.45個百分比的固定圖樣雜訊、以及在16次的虛多重取樣技術下減少時間雜訊至1.09毫伏特的方均根電壓。

This Thesis presents a readout integrated circuit (ROIC) with inverter-based capacitive transimpedance amplifier (CTIA), in-pixel correlated double sampling (CDS) mechanism, and pseudo-multiple sampling technique for infrared focal plane array (IRFPA). The proposed inverter-based CTIA with a coupling capacitor, executing auto-zeroing technique to cancel out the varied offset voltage from process variation, is used to substitute differential amplifier in conventional CTIA. The tunable detector bias is applied from a global external bias before exposure. This scheme not only retains stable detector bias voltage and signal injection efficiency, but also reduces the pixel area as well. CDS is a useful signal processing method to suppress the low frequency noise and fixed pattern noise (FPN). Compared to the conventional CDS, this in-pixel CDS is achieved by only one capacitor and a single switch connected to external reference voltage. Pseudo-multiple sampling technique is adopted to reduce the temporal noise of readout circuit. The noise reduction performance is comparable to the conventional multiple sampling operation without need of longer readout time proportional to the number of samples
A prototype 55×65 pixel imager employed these schemes has been designed and fabricated in 0.18μm CMOS technology. The functions and performance of the proposed readout circuit have been verified by experimental measurements at 3.3V supply voltage. It achieves a 12μm×12μm pixel size, a frame rate of 72 fps, a FPN of 0.45%, and a temporal readout noise of 1.09mVrms (with 16 times of pseudo-multiple sampling), respectively.

[1] N. Itoh, K. Yanagisawa, T. Ichikawa, K. Tarusawa, and H. Kataza, “Kiso observatory near-infrared camera with a large format array,” proceedings of the SPIE, Infrared Technology XXI, vol. 2552, pp. 430-437, 1995.
[2] K. Murari, R. Etienne-Cummings, N.V. Thakor, and G. Cauwenberghs, “A CMOS in-pixel CTIA high-sensitivity fluorescence imager” Trans. Biomedical Circuits and Systems, vol. 5, issue 5, pp. 449-458, 2011.
[3] D. A. Scribner, M. R. Kruer, and J. M. Killiany, “Infrared focal-plane array technology,” Proceeding of IEEE, vol. 76, no. 1, pp.66-85, Jan 1991.
[4] K. Schreiner, “Night vision: infrared takes to the road,” IEEE Computer Graphics and Applications, vol. 19, issue 5, pp. 6-10, 1999.
[5] G. Jun, C. Zhongjian, L. Wengao,C. Wentao, J. Lijiu, “Correlated double sample design for CMOS image readout IC,” IEEE ICSICT, vol. 2, pp. 1437-1440, 2004.
[6] L. Yong, K. Koh, K. Kim, H. Yang, J. Kim, Y. Jeong, S. Lee, H. Lee, S. H. Lim, Y. Han, J. Kim, J. Yun, “A 1.1e- temporal noise 1/3.2-inch 8M pixel CMOS image sensor using pseudo-multiple sampling,” IEEE ISSCC, pp. 396-397, 2010.
[7] H. H. Chen, and C. C. Hsieh, “An inverter-based capacitive trans-impedance amplifier readout with offset cancellation and temporal noise reduction for IR focal plane array,” International Symposium on Photoelectonic Detection and Image, vol. 8907, 2013.
[8] J. Ohta, “Smart CMOS imager sensors and applications,” CRC Press
[9] P. J. W. Noble, “Self-scanned silicon image detector arrays,” IEEE Trans. Electron Devices, vol. 15, no. 4, pp. 202-209. Apr. 1968.
[10] E. Fossum, “Active pixel sensors: are CCD’s dinosaurs?” proceedings of the SPIE, Charged-Coupled Devices and Solid State Optical Sensors III, vol. 1900, pp. 30-39, 1993.
[11] J. E. Eklund, C. Svensson, and A. Astrom, “VLSI implementation of a focal plane image processor – a realization of the near-sensor image processing concept,” IEEE Trans. Very Large Scale Integration Syst., vol. 4, no. 3, pp. 322-335, Sep. 1996.
[12] R. Guidash, T. H. Lee, P. Lee, D. Sackett, C. Drowley, M. Swenson, L. Arbaugh, R. Hollstein, F. Shapiro, and S. Domer, “A 0.6um CMOS pinned photodiode color imager technology,” Proc. Int. Electron Devices Meeting Tech. Dig., pp. 927-929, Dec. 1997.
[13] A. El Gamal, and H. Eltoukhy, “CMOS image sensors,” IEEE Circuit Devices Mag., vol. 21, no. 3, pp. 6-20, May/Jun. 2005.
[14] D. G. Chen, D. Matolin, A. Bermak, and C. Posch, “Pulse-modulation imaging – review and performance analysis,” IEEE Trans. Biomedical Circuits and System, vol.5, no.1, pp. 64-82, Deb. 2011.
[15] L. Yao, “CMOS readout circuit design for infrared image sensors,” proceedings of the SPIE, Imaging Detectors and Applications, vol. 7384, 73841B, 2009.
[16] K. Chow, J. P. Rode, D. H. Seib, and J. D. Blackwell, “Hybrid infrared focal-plane arrays,” IEEE Transactions on Electron Devices, vol. 29, no. 1, pp. 3-13, Jan 1982.
[17] L. J. Kozlowski, W. V. McLevige, S. A. Cabelli, A. H. B. Vanberwyck, D. E. Cooper, E. R. Blazejewski, K. Vural and W. E. Tennant, “Attainment of high sensitivity at elevated operation temperature with staring hybrid HgCdTe-on-sapphire focal plane arrays,” Opt. Eng., vol. 33, no. 3, pp. 704-715, 1994.
[18] A. M. Fowler, R. G. Probst, J. P. Britt, R, R, Joyce, and F. C. Grillett, “Evaluation of an indium antimonide hybrid focal plane array for ground-based infrared astronomy,” Opt. Eng., vol. 26, no. 3,pp. 232-240, 1987.
[19] N. Bluzer, and R. Stehik, “Buffered direct injection of photocurrents into charge coupled devices,” IEEE Journal of Solid-State Circuits, vol. 13, no. 1, pp. 86-92, Feb. 1987.
[20] P. Norton, “Infrared image sensors,” Opt. Eng., vol. 30, no. 11,pp. 1649-1660, 1991.
[21] C. C. Hsieh, C. Y. Wu, F. W. Jih, and T. P. Sun, “Focal-plane-array and CMOS readout techniques of infrared imaging systems,” IEEE Trans. on Circuits and Systems for Video Technology, vol. 7, pp. 594-605, Aug. 1997.
[22] C. C. Hsieh, C. Y. Wu, F. W. Jih, T. P. Sun, and H. Cheng, “A new CMOS readout circuit design for the IR FPA with adaptive gain control and current-mode background suppression,” IEEE International Symposium on Circuit and System, vol. 1, pp. 137-140, 1996.
[23] C. Staller, L. Ramiirez, C. Niblack, M. Blessinger, and W. Kleiinhans,“A radiation hard, low background multiplexer design for spacecraft imager applications,” proceedings of the SPIE, Infrared Readout Electronics, vol. 1684, pp. 175-181, 1992.
[24] Hoffman, “Capacitor transimpedance amplifier (CTIA) with shared load,” US patent 6252462, 2001.
[25] L. W. Huang, “A 1.8V readout integrated circuit with adaptive transimpedance control amplifier for focal plane arrays,” National Tsing Hua University, Oct. 2011.
[26] R. J. Kansy, “An response of a correlated double sampling circuit to 1/f noise,” IEEE Journal of Solid-State Circuit, vol. 15, no. 3, pp. 373-375, Jun 1980
[27] I. M. Hafez, G. Ghibauso, and F. Balestra, “A study of flicker noise in MOS transistors operated at room and liquid helium temperatures,” Solid State Electronics, pp. 1525-1529, 1990.
[28] W. V. Backensto, and C. R. Viswananathan, “Bias-dependent 1/f noise model of a MOS transistor,” Proc. IEEE, pp. 87-92, 1980.
[29] J. F. Johnson, “Hybrid infrared focal plane signal and noise model,” IEEE Trans. Electron Devices, pp. 96-108, 1999.
[30] X. Chen, “The noise analysis and its suppression in CMOS ROIC for microbolometric infrared focal plane array,” Proc. SPIE, vol. 7135, Nov. 2008.
[31] Orly Yadid-pecht, and Ralph Etienne-Cummings, “CMOS imagers from phototransduction to image processing,” KLUWER ACADEMIC PUBLISHERS, 2004.
[32] A. Huggett, C. Silsby, S. Cami, and J. Beck, “A dual-conversion-gain video sensor with dewarping and overlay on a single chip,” ISSCC Dig. Tech. Papers, pp. 52-53, Feb. 2009.
[33] S. Matsuo, T. Bales, M. Shoda, S. Osawa, B. Almend, Y. Mo, J. Gleason, T. Chow, I. Takayanagi, “A very low column FPN and row temporal noise 8.9 M pixel, 60 fps CMOS image sensor with 14bit column parallel SA-ADC,” IEEE Symposium on VLSI Circuits, pp. 138-139, June 2008.
[34] S. Kawahito, and N. Kawai, “Column Parallel Signal Processing Techniques for Reducing Thermal and Random Telegraph Noises in CMOS image sensor,” International Image Sensor Workshop, pp.226-229, June 2007.
[35] S. Kawahito, S. Suh, T. Shirei, S. Itoh, and S. Aoyama, “Noise Reduction Effects of Column-Parallel Correlated Multiple Sampling and Source-Follower Driving Current Switching for CMOS Image Sensors,” International Image Sensor Workshop, June 2009.
[36] K. Nagaraj, J. Vlach, T. R. Viswanathan, and K. Singhal, “Switched-capacitor integrator with reduced sensitivity to amplifier gain,” Electronics Lett., vol. 22, issue 21, pp. 1103-1105, 1986.
[37] Y. Chae, and G. Han, “Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator,” IEEE Journal of Solid-State Circuits, vol. 44, issue 2, pp. 458-472, 2009.
[38] M. Furuta, Y. Nishikawa, T. Inoue, and S. Kawahito, “A high-speed, high sensitivity digital CMOS image sensor with global shutter and 12-bit column-parallel cyclic A/D converters,” IEEE Journal of Solid-State Circuits, vol. 42, issue 4, pp. 766-774, 2007
[39] K. W. Cheng, C. Yin, C. C. Hsieh, W. H. Chang, H. H. Tsai, and C. F. Chiu, “Time-delay integration readout with adjacent pixel signal transfer for CMOS image sensor,” International Symposium on VLSI-DAT, pp. 1-4, 2012.
[40] W. F. Chou, S. F. Yeh, and C. C. Hsieh, “A 143dB 1.96% FPN linear-logarithmic CMOS image sensor with threshold-voltage cancellation and tunable linear range,” IEEE Sensors, pp. 1-4, 2012.
[41] L. W. Huang, C. C. Hsieh, W. H. Chang, Y. Z. Juang, and C. F. Chiu, “A 1.8V readout integrated circuit with adaptive transimpedance control amplifier for IR Focal Plane Arrays,” IEEE Sensors, pp. 1145-1148, 2011.
[42] R. Xu, B. Liu, and J. Yuan, “A 1500 fps highly sensitive 256×256 CMOS imaging sensor with in-pixel calibration,” IEEE Journal of Solid-State Circuits, vol. 47, issue 6, pp. 1408-1418, 2012