研究生: |
陳煜智 Chen, Yu Jhih |
---|---|
論文名稱: |
應用於連續微流體晶片上之基因邏輯電路排程與優化 Scheduling and Optimization of Genetic Logic Circuits on Flow-Based Microfluidic Biochips |
指導教授: |
何宗易
Ho, Tsung Yi |
口試委員: |
黃俊達
Huang, Juinn Dar 陳宏明 Chen, Hung Ming |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊系統與應用研究所 Institute of Information Systems and Applications |
論文出版年: | 2016 |
畢業學年度: | 105 |
語文別: | 英文 |
論文頁數: | 33 |
中文關鍵詞: | 微流體晶片 、合成生物學 |
外文關鍵詞: | Microfluidic biochip, Synthetic biology |
相關次數: | 點閱:4 下載:0 |
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合成生物學透過生物細胞來進行基因電路的製造,當製造大型基因電路時,串擾效應(Crosstalk effect)將干擾實驗精準度,造成錯誤實驗結果產出,為了減低串擾效應的影響,現今的方法為在連續微流體晶片上製作隔離反應室,將反應細胞與其輸入輸出流動方向進行限制,藉此來減低串擾效應的影響;連續微流體晶片使用微型設備控制流體,藉此獲得較高的控制精確度,因此,在其上進行合成生物學實驗可以獲得較高的可信度以及擴展性。現今的實現方式將生物邏輯閘的反應時間統一,然而每個邏輯閘的反應時間皆不相同,此方式將導致不必要的實驗時間浪費,本論文提出一個應用於此的新排程方式,將不同邏輯閘的反應時間納入考量,縮短整體實驗耗時,本論文另外也縮減控制埠的使用數量,使其數量控制在硬體限制內,並且優化流體層及控制層的繞線結果,用以降低設計成本。
Synthetic biologists design genetic logic circuit using living cells.
A challenge in this task is the difficulty in constructing bigger logic circuits with several living cells due to the crosstalk effect among the biological cells.
In order to remove the crosstalk effect, current practice is to use separate chambers on a flow-based microfluidic biochip to isolate each reaction zone.
A flow-based microfluidic biochip can provide high precision control using microscale devices for the flow of biological substances.
Hence, it can contruct more reliable and scalable genetic logic systems for synthetic biology experiments.
The state-of-the-art technqiue assumes the reaction rates of different genetic logic gates are identical.
This assumption is pessimistic as each genetic logic gate has the reaction rate different from others.
Hence, it will cause unnecessary waiting time for fast logic gates and this, in turn, lengthen the whole experiment completion time significantly.
In this thesis, we propose a new scheduling scheme for genetic logic circuits in flow-based microfluidic biochips considering different reaction time of each logic gate.
Simulation results show that the proposed scheme reduces the experiment completion time.
We further minimize the number of control valves and optimize the routing of flow and control layers in the chip layout, which in turn reduces the design cost.
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