在個人通訊設備的普及之後，無線通訊的頻寬就愈來愈受到限制。ITU-T中的VCEG (Video Coding Expert Group) 因此發展了H.26L技術，延續了H.263的優點，並加以利用高度壓縮效率的技術來降低傳輸用的位元數。然而在此技術下若要達到即時的影像壓縮效果(每秒30張)，需要非常高速的處理器作運算。同時，移動向量的估計所需要的運算量，佔用了影像壓縮程式龐大的計算量。因此在這篇論文中，提出了一個針對H.26L所設計的全域搜尋移動估計設計，以作為整個影像壓縮系統的協同處理器。對於H.26L中關於移動估計的特性，處理單元的設計必須考慮到七種比對區塊大小的組合，以及五張參考影像的延伸性。採用全域搜尋區塊提供較高的影像品質，並且較具有規則性，適合硬體實作。因此我們採用了處理單元陣列搭配內建記憶體以處理全域搜尋所需要的大量的資訊，在降低了外部記憶體的存取次數同時，也能使得晶片有效率的運作。此晶片是採用cell-based設計流程，以及0.35微米單層多晶矽三層金屬層的互補式金氧半場效電晶體製程技術，工作頻率設定在60MHz。在五張參考影像的需求下，可以達到最大輸出率每秒29張QCIF影像。

Recently, many video encoding standards are applied to the communication devices. In most compression standards, such as H.263, H.26L, MPEG2 and MPEG4, motion estimation exploits large amount of computation power. An emerging video encoding technique, H.26L, achieves a bit rate reduction of about 30% with the same quality as in H.263 version 2. However, the encoding time is about three times longer because of complex operations. In this thesis, a new architecture for full-search variable-size block-matching motion estimation was proposed. The processing element in PE array can deal with variable block sizes in 7 macroblock types in H.26L. Besides, with the consideration of the dataflow and memory accessing, all components in the architecture can work efficiently. The chip implemented by CIC 0.35 μm 1-Poly 4-Metal CMOS technology works at 60 MHz. The Maximum throughput is 29 frames per second in QCIF format with 5 reference frames and 7 block types at 60 MHz.

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