近年來，非揮發性記憶體相當普及且應用極廣，其中快閃記憶體提供了成本低廉、大容量且無須供給電源的資料儲存，很快地成為非揮發性記憶體中的主流。然而，快閃記憶體製程技術雖成熟，其需高壓又耗時的寫入抹除週期使這些優勢失色許多；更糟的是，快閃記憶體於製程微縮時遭遇困難，低壓環境下的微弱電流、閾值電壓變異大且需要高壓防護都限制了設計彈性。相較之下，新興非揮發性記憶體能有效緩解那些隱憂，極具潛力取代快閃記憶體，成為下世代非揮發性儲存的解決之道。
接觸點電阻式記憶體(Contact ReRAM)具較低的寫入電壓與功耗、更快的寫入週期，同時完全相容於CMOS純邏輯製程，在各操作電壓下皆呈現不錯的特性，因此對我們低功耗的需求極具吸引力。然而，接觸點電阻式記憶體的小阻率及偏高的低阻態阻值也使其感測困難。為解決上述新衍生的問題讓此作更適合低壓操作，我們提出一個具偏移抑制及裕度增強架構的感測放大器來提升低壓環境的操作速度及良率。我們透過自動調零機制實現飄移抑制架構，能有效地將跳閘點歸零以減少感測放大器偏移，在1V獲得75.5%的提升，於0.3V獲得65%的提升。裕度增強架構透過耦合電容放大輸入差，減少低壓環境下冗長的位元線電壓發展時間，0.3V元件電流變得十分微弱時尤其明顯。縱使操作於0.5V以下且受時控偏移影響時其效率會衰減，但仍維持55%左右的改良。同時使用兩架構，覆蓋4個標準差的整體感測速度約提升15%；良率方面，僅需20mV的輸入差即可達到4個標準差覆蓋。
我們在256Kb的接觸點電阻式記憶體晶片中實現此提案，於台積65奈米標準CMOS製程下製造。量測結果和預期相去不遠，偏移電壓受抑制，在1V時低於40mV，0.3V時低於16.7mV。4個標準差覆蓋下的存取時間分別於1V、0.5V、0.3V提升至6.28ns、34.6ns及360ns。

These years, non-volatile memory is popular and widely employed in various applications. Flash memory provides cost-effective large capacity power-off storage; soon it becomes the mainstream of non-volatile memory. Although technology of Flash memory is mature, demands for high program/erase voltage and long program/erase cycle make those advantages a little gloomy. Even worse, Flash is confronted with tough challenges of scaling; issues of small cell current ICELL under low supply voltage, great VTH variation and high voltage protection during program/erase limit the design flexibility. On the contrary, emerging non-volatile memory can significantly relax those concerns, and they have great potential to replace the Flash memory, being a promising candidate as the next generation solution of non-volatile storage.
With characteristics of lower program voltage/power, faster programming cycle and CMOS logic process compatible, CRRAM performs excellent from standard to low supply voltage. Hence, it is very attractive to us for low power. However, CRRAM suffers from small R-ratio and high resistive LRS state, which increase the difficulty of sensing. In order to deal with the arising issues described above for better fitting low supply voltage application, we propose a SA with Offset Suppression and Margin Enhancement scheme to improve the speed and yield under scaled VDD environment. Offset Suppression Scheme is realized by Auto-Zero technique, which can significantly reduce SA offset by VTRIP zeroing, achieving 75.5% and 65% improvement at 1V and 0.3V supply voltage respectively. Margin Enhancement Scheme can enlarge the input swing by coupling capacitor, reducing lengthy VBL developing time especially when ICELL becomes tiny at 0.3V. Although the efficiency decays under 0.5V VDD with timing skew, wet still gets 55% margin expansion. With these two scheme, overall sensing speed with 4-Sigma coverage is around 15% improved; as for yield, it requires only 20mV input difference to cover 4-Sigma variation.
Proposed SA is implemented in a 256Kb CRRAM macro, which is fabricated in TSMC 65nm Generic CMOS process. Measurement results roughly match our prediction; the VOS is suppressed under 40mV at 1V and 16.7mV at 0.3V. Access time with 4-Sigma coverage is improved to 6.28ns, 34.6ns and 360ns at 1V, 0.5V and 0.3V respectively.

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